We developed a prototype of a new kind of microprocessor, the OpenTransputer

[w34]

Hi everyone,

We are two final year students at the University of Bristol, UK and we developed a new microprocessor, the OpenTransputer (http://opentransputer.org) for our final year dissertation. The OpenTransputer is based on the Transputer developed at Inmos in the 1980s. Their lead designer, Professor David May, was the supervisor of our project.

At the moment we are at a stage where want to gauge interest in this project, which is why we've started attending conferences, and why we are trying to get the word out by posting here.

We're happy to take any questions and we'll be checking back here quite regularly!

We're also on Facebook (https://www.facebook.com/OpenTransputer) and Twitter (https://twitter.com/opentransputer), just in case our website crashes from all the traffic you guys generate ;D.

[throwaway000002]

Is there anything novel with respect to the original Transputer that you've decided to introduce while implementing your design?

As I am not familiar with the Transputer, how does the on-chip communication structure compare to the work of Xmos and their Xcore architecture? I believe David May was involved with that as well.

Looking forward to reading your dissertation.

[w34]

By the way our dissertation is online and easy to access: http://www.opentransputer.org/wp-content/uploads/2015/06/dis...

To answer the XMOS question: XMOS's design was quite heavily influenced by the original Transputer and therefore they are quite similar. The one major difference to note that we're a stack machine.

XMOS uses registers and is limited to 8 threads per core in most of their architectures. So if you suddenly want to go large and build a massively distributed system you might have to take into consideration that on each individual XMOS chip you can only run 8 processes at a time and might have to change your software.

With our stack machine approach you can run the same program that may basically consist of an unlimited number of processes (as long as you have enough memory to store them that is) on either just one single Transputer or -- with no change to your program -- on an array of (unlimited) Transputers with each Transputer running one process.

So the entire architecture makes scaling easier.

I also think the way we talk to peripherals is different to XMOS but I'd have to check up on that. I've used XC and XMOS boards before as part of my degree here at Bristol but I never connected peripherals and then interfaced them on their boards.

[w34]

Yes!

There are quite a few changes we made on the architectural and microarchitectural level. Our dissertation and the presentation slides do mention this but I'll give you the gist of it:

We replaced the existing serial communication links with a single link that connects to a network of switches that are arranged in a Benes fashion. This allows for a very scalable way of building networks and is actually used in telecommunications systems. Our supervisor, Professor David May actually gave us the idea. Seemed pretty smart to me compared to other ways of building large networks.

We also introduced a new way of interfacing with peripherals (I/O), sensors and other things that might be useful to have if you're developing a piece of IoT hardware. And as I said we use the same message passing mechanism to interface with them that we also use for communication.

We also made lots of changes on the microarchitectural side: We went away from a microcoded design and became more akin to RISC by using hard wired logic.

[slasaus]

Are you guys familiar with lowRISC.org and is your work maybe partly overlapping with their work? I read that your MISC design falls somewhere in the middle between RISC and CISC.

[w34]

Interesting question! Today is the first time I've heard of this particular RISC project, but at a conference we recently attended (http://oshug.org/event/42) I actually got talking to someone from Cambridge who's also working on his own open source RISC implementation (shout out to BERI: An open RISC softcore for research and experimentation).

Being Open Source is actually not our main differentiator from what's already out there in the processor market. Our main differentiator is in the very architecture of the processor, and perhaps interestingly the architecture also affects the kinds of businesses and projects we're targeting.

The OpenTransputer uses the Transputer instruction set, which is 30 years old, much like a current Intel or ARM processor use instructions sets that in their original form are also 30 years old.

The Transputer instruction set architecture (ISA) is very unique in that it is a stack machine, much like Java actually, just in hardware! On the microarchitecture level both the original Transputer and OpenTransputer come with inbuilt memory and communication links.

The Transputer is very closely tied to Occam, a language based on CSP, which means it uses message passing for everything. So we're much different from current RISC and CISC processors in that we don't use shared memory but message passing to achieve multicore. It makes concurrency simpler and allows for simple and large scaling (in particular for embarrassingly parallel problems).

The intricate nature of the Transputer ISA actually made us come to the conclusion that we should be targeting the IoT market, you know, all these small devices that both the maker community but also big businesses are interested in. Because what we keep hearing is how hard it is to interface with multiple processors and external devices.

We actually made the way you communicate with peripherals (I/O) the same as how you communicate with processors: Message passing. It takes a line to set a pin high, it could not be easier.

Please keep asking if there's anything unclear in there, because I'm sure I left something relevant out!

There's actually a video of that conference I mentioned somewhere, that would probably be helpful in explaining what's going on regarding the Architecture.