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Create Your Own CPU on an FPGA

118 points| kardashev | 10 years ago |embeddedmicro.com | reply

20 comments

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[+] farresito|10 years ago|reply
Some guy started a series some weeks ago on designing a CPU for an FPGA: http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-...

For those interested in a more complex processor, RISC-V seems to be a processor on par with ARM in terms of features: http://riscv.org/

[+] kjs3|10 years ago|reply
Both of these are excellent projects to check out if you're interested in such things. And, bonus, the RISC-V folks have produced an open source, modern manufacturing process, 1GHz core that I hope is a game changer in open source hardware. It's not quite on par with ARM (lacking the billions in investment), but it's in the ballpark and it's the real deal. Definitely worth keeping up with.
[+] kardashev|10 years ago|reply
Does anyone have knowledge about the comparison of different FPGA boards?

I've seen the Mojo v3 from Embedded Micro, the Papilio line of dev boards, and the miniSpartan6+ from Scarab Hardware.

It looks like all these dev boards are pretty similar since they use almost identical xilinx chips. Ideally, I'd like to find a board for which there is a robust community, good support, lots of examples, and has enough capacity/performance to take on more complicated projects with increased learning/skill.

I'm leaning towards the Mojo v3 board, since it seems very easy and has shields to expand capability, but does anyone have any experience, recommendations, or "I wish I had known..." stories for FPGA development?

[+] aprdm|10 years ago|reply
Basically, go with the market leaders, either altera or xilinx.

Altera DE brand is used in universities all over the world and they have their alteraforum (which is really old fashioned but does the job).

I would go with a DE2 or something like that. (Which has a Cyclone IV)

[+] planteen|10 years ago|reply
I like the Avnet MicroZed which is built around a Xilinx Zynq. The Zynq is a latest generation FPGA and dual core ARM on a chip. There's a decent community and all the development tools are free.
[+] caberus|10 years ago|reply
almost 10 years ago i wrote vhdl code on spartan series cards, and that time i noticed that Xilinx IDE was really far from Visual Studio. hope things have changed since then. So my suggestion is to check development tools as well, if you dont need the "best" board just, but also the ease of development
[+] pjc50|10 years ago|reply
... using the "Lucid" HDL, which at first glance seems like a de-crufted Verilog.
[+] mcguire|10 years ago|reply
That's a good thing, right?
[+] zeusk|10 years ago|reply
I'll just leave this here: https://github.com/zeusk/CS242

I did this during my sophomore year, didn't care much about implementing a proper memory implementation as that was way beyond the scope of our course.

[+] scottmwinters|10 years ago|reply
Every Computer Engineering undergrad is rejoicing somebody just did their project for them.
[+] rational_indian|10 years ago|reply
This is not written in Verilog/VHDL. I doubt they will be able to pass this off as their own work.
[+] m3talridl3y|10 years ago|reply
Does anyone have any tips on determining if a given CPU core will fit onto a given FPGA? Most of the boards in the hobbyist price range seem kinda ... underwhelming.
[+] aprdm|10 years ago|reply
You can just download the CAD free version (Quartus II or ISE) and compile it for a target FPGA board.
[+] alain94040|10 years ago|reply
No discussion of CPU design is complete without trying to run your design as fast as possible. That's how people discovered that pipelining is good, and a flat implementation (such as the one in that code) is slow.
[+] Gladdyu|10 years ago|reply
Don't forget simplicity - their goal is learning by creating a "super basic CPU" for which you can write "some assembly". Including pipelining in this design would distract from the main purpose.

It would make a nice topic for a follow-up tutorial though.

[+] sklogic|10 years ago|reply
There is a trade-off between performance and area. Pipelined designs are bigger (not least because of all that pipeline registers).