Intel's Management Engine (which is on all modern Intel chips) acts as a unverifiable second processor with memory and network access running closed proprietary software. Its existence prevents any sort of security from state level actors.
Is that anything like the "secure enclave" we've heard so much about re: Apple iPhone, at least the current versions? Not sure how much benefit or utility that would add to a server vs. phone CPU, but it's interesting anyway.
The critical issue here is whether this is really "open".
The x86 platform, like most processors, has a documented instruction set and software loading process. (There are undocumented corners, but the "front door" is open). Whereas historically almost all FPGAs have had fully closed bitstream formats and loading procedures. This necessitates the use of the manufacturer's software which is (a) often terrible and (b) usually restricted to Verilog and VHDL.
If Intel ship a genuinely open set of tools, then all manner of wonderful things could be built on the FPGA, dynamically. That requires being open down to the bitstream level, which also requires that the system is designed so that no bitstream can damage the FPGA.
To me this is most interesting not at the server level but at the ""IoT"" level; if they start making Edison or NUC boards that expose the FPGA to a useful extent.
(a) you don't have to use any vendor's IDE, only their placement and synthesis tools which all support command line (b) Verilog and VHDL are the only two dominant HDL languages.. what other language would you want to program in??
AMD HSA is more compelling. These look like they will be just as hard to program as adding in an accelerator card, only the bandwidth between the CPU and the FPGA is higher. Everything is merging into an amorphous blob, FPGAs have been adding hard blocks for years, GPUs have been adding scalar accelerators. The vector and the scalar, the hardwired and the adaptable are all becoming one. Hell, even the static languages are adding dynamism and the dynamic languages are adding types. Floating point is becoming succinct [0]. Computation is becoming a continuum.
Programmable logic on chips will be INCREDIBLE for the field of intrinsic hardware evolution, which is a slowly emerging science. This is huge for the field of AI and electronics.
I've been waiting to see this kind of thing for years, ever since I read Adrian Thompson's work on evolution with FPGAs, in which he:
The field has crawled along pretty slowly since then as far as I can tell.
However, this could be a HUGE thing for computing; developers would finally have a way to create hardware that interacts directly with the physical world in ways we haven't thought of yet. As a small example, Thompson's work revealed circuits that were electromagnetically coupled in novel ways but not connected to the circuit path, yet were required for the circuit to work. Using evolution, in time we should be able to come up with unique solutions to hardware problems not envisaged by human designers.
There were many years when any hardware computing acceleration card failed pretty quickly because CPUs were advancing so rapidly hardware could not keep up. Apparently we have reached an end to this. With GPUs, and things like this FPGA integration, hardware matters again.
Before the difference between highly optimized code and ok code was maybe 2-3x speedup. Roughly one Moore's law doubling. With heterogeneous computing that is more like 20-30x or more. And Moore's law is dead! This will change a loot in the IT world (More servers are the solution, developer time is more expensive then computer time, etc..). Learn C, down on the metal programming is back, the future is heterogeneous parallel computing.
Programable logic on the die sounds like a great thing in principle, but the place where it really comes into its own is doing I/O work. Network/disk acceleration, offload, encryption. This is where hardware (which is slow and wide), but is reconfigurable over software lifecycle (e.g. protocols, file systems etc which change rapidly) would be a benefit. So the real question is, what is the I/O capability of one of these things? Will the high speed transceivers be exposed in a way that I/O devices can talk directly to it, or will they all need to go through a slow, high latency PICe interconnect. If the later, then I would predict a chocolate tea-pot in the making.
One can program the NIC to DMA packets directly info the address space allot for FPGA. Once setup, the FPGA should be able to get hold the packets and start processing completely without a single CPU cycle use on data plane.
Finally, this technology is gaining acceptance. Leopard Logic and others tried this about 15 years ago but Moore's Law and Dennard Scaling were still going so CPU+FPGA didn't take hold. I'm not sure exactly how Intel is going to implement this but the predecessors had multiple configuration planes so that the FPGA could be switched from Config1 to Config2 in nanoseconds (e.g. TCP offload, then neural network calculation, then TCP offload, etc) and had some automatic compiler support.
My question is what market is going to be driving this? Who will want to buy this, and how deep are their pockets? Is this a niche product for a handful of applications, or something we'll see in every PC in 5 years?
The GPU was successful because it had a killer app: Gaming. What's the killer app for the FPGA going to be?
Server side things. Machine learning, on cpu die network switch, various forms of offloading (SSL, compression, possibly hypervisor stuff).
It will be awhile before it shows up in consumer gear, as the use cases are not there yet. Consumers may still benefit as when someone figures out something amazing for it to do, they will get a hardened version of it.
Anything reasonably parallel that needs high throughput or low latency can benefit from an FPGA. I would probably find use for one in audio/video processing offload for media production. If the FPGAs entered consumer parts, games could use them for I/O offloading to give gamers a latency edge, or process thousands of parallel game simulation elements in ways maybe GPUs can't help.
Microsoft and (apparently) Intel think the killer app is in accelerating datacenter apps. I think it's more likely to be something nobody is doing yet.
Custom full disk encryption implementations, like crypto acceleration for an algorithm such as norx.io. Or custom video codec acceleration for streaming it rendering. Or physics simulation acceleration.
More precisely, to put AI on smart phones. Neural network is cheaper on FPGA. You can switch between AIs (voice/image/text recognition, games, etc) quickly and update them over the internet.
I think that along the hardware problem of integrating both chips on the same die, the other problematics are about their programmation.
We have a pretty advanced abstraction when it comes to CPU nowadays, but looking at some code to program FPGAs we definitely can see that it's not that simple for developers to enter this world.
There's a bit of a bootstrapping/catch-22 problem with FPGAs. Right now they are all mostly proprietary hardware with proprietary development tools, so only the most demanding niches will invest. Because they only see niche use, nobody invests in more general tools.
If Intel added a fully open, fully specified FPGA to a CPU, that anyone could write tools for, that could change.
> the hardware problem of integrating both chips on the same die
Mostly a non-issue. Multi-chip packages have been around for decades. Intel has been putting DRAM chips onto their CPU packages (for their Iris Pro graphics chips) for a few generations now; Core i CPUs also have on-chip PCIE controllers together with their QPI inter-cpu interface, if for some reason the latter can't be made to work with FPGAs.
[+] [-] trengrj|10 years ago|reply
Intel's Management Engine (which is on all modern Intel chips) acts as a unverifiable second processor with memory and network access running closed proprietary software. Its existence prevents any sort of security from state level actors.
[+] [-] winter_blue|10 years ago|reply
[+] [-] jrapdx3|10 years ago|reply
[+] [-] Ericson2314|10 years ago|reply
[+] [-] moonbug|10 years ago|reply
[deleted]
[+] [-] pjc50|10 years ago|reply
The x86 platform, like most processors, has a documented instruction set and software loading process. (There are undocumented corners, but the "front door" is open). Whereas historically almost all FPGAs have had fully closed bitstream formats and loading procedures. This necessitates the use of the manufacturer's software which is (a) often terrible and (b) usually restricted to Verilog and VHDL.
If Intel ship a genuinely open set of tools, then all manner of wonderful things could be built on the FPGA, dynamically. That requires being open down to the bitstream level, which also requires that the system is designed so that no bitstream can damage the FPGA.
To me this is most interesting not at the server level but at the ""IoT"" level; if they start making Edison or NUC boards that expose the FPGA to a useful extent.
[+] [-] bravo22|10 years ago|reply
[+] [-] sitkack|10 years ago|reply
[0] http://johngustafson.net/unums.html
[+] [-] btown|10 years ago|reply
[+] [-] unknown|10 years ago|reply
[deleted]
[+] [-] arc776|10 years ago|reply
I've been waiting to see this kind of thing for years, ever since I read Adrian Thompson's work on evolution with FPGAs, in which he:
"Evolved a tone discriminator using fewer than 40 programmable logic gates and no clock signal in a FPGA" (slides: https://static.aminer.org/pdf/PDF/000/308/779/an_evolved_cir...)
EDIT: Full paper: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.50....
The field has crawled along pretty slowly since then as far as I can tell.
However, this could be a HUGE thing for computing; developers would finally have a way to create hardware that interacts directly with the physical world in ways we haven't thought of yet. As a small example, Thompson's work revealed circuits that were electromagnetically coupled in novel ways but not connected to the circuit path, yet were required for the circuit to work. Using evolution, in time we should be able to come up with unique solutions to hardware problems not envisaged by human designers.
This is really exciting.
[+] [-] mchahn|10 years ago|reply
[+] [-] 0x07c0|10 years ago|reply
Before the difference between highly optimized code and ok code was maybe 2-3x speedup. Roughly one Moore's law doubling. With heterogeneous computing that is more like 20-30x or more. And Moore's law is dead! This will change a loot in the IT world (More servers are the solution, developer time is more expensive then computer time, etc..). Learn C, down on the metal programming is back, the future is heterogeneous parallel computing.
[+] [-] oldmanjay|10 years ago|reply
[+] [-] deadgrey19|10 years ago|reply
[+] [-] srcmap|10 years ago|reply
[+] [-] ShinyCyril|10 years ago|reply
[+] [-] juicenx|10 years ago|reply
They do exactly this in a programmable PCIe card and custom ASIC.
[+] [-] CoffeeDregs|10 years ago|reply
[+] [-] csense|10 years ago|reply
The GPU was successful because it had a killer app: Gaming. What's the killer app for the FPGA going to be?
[+] [-] extrapickles|10 years ago|reply
It will be awhile before it shows up in consumer gear, as the use cases are not there yet. Consumers may still benefit as when someone figures out something amazing for it to do, they will get a hardened version of it.
[+] [-] nitrogen|10 years ago|reply
[+] [-] sapek|10 years ago|reply
[+] [-] kbob|10 years ago|reply
[+] [-] Ericson2314|10 years ago|reply
The program to reprogram them every few seconds (genetic algorithms?) sounds more interesting.
[+] [-] Natanael_L|10 years ago|reply
[+] [-] qznc|10 years ago|reply
More precisely, to put AI on smart phones. Neural network is cheaper on FPGA. You can switch between AIs (voice/image/text recognition, games, etc) quickly and update them over the internet.
[+] [-] sklogic|10 years ago|reply
[+] [-] crmd|10 years ago|reply
[+] [-] jstoja|10 years ago|reply
[+] [-] nitrogen|10 years ago|reply
If Intel added a fully open, fully specified FPGA to a CPU, that anyone could write tools for, that could change.
[+] [-] Ericson2314|10 years ago|reply
The actual problem (as stated in the other comments) is that the tooling is all proprietary (huge and scary) and has received NO love.
[+] [-] floatboth|10 years ago|reply
There are even vendors marketing PCI FPGA cards as "OpenCL FPGA cards": http://www.nallatech.com/solutions/fpga-accelerated-computin...
[+] [-] creshal|10 years ago|reply
Mostly a non-issue. Multi-chip packages have been around for decades. Intel has been putting DRAM chips onto their CPU packages (for their Iris Pro graphics chips) for a few generations now; Core i CPUs also have on-chip PCIE controllers together with their QPI inter-cpu interface, if for some reason the latter can't be made to work with FPGAs.
[+] [-] PaulHoule|10 years ago|reply