[Andrey_Filippov]

Yes, you are absolutely right about "repeatedly solved problems", so it is definitly one in the series of "yet another ...". I'll try your program on our project files to see what registers it can extract from it. I'm assuming that there is no perfect universal solution, and I agree that Verilog-to-C (just having C in the back of your mind while working on the FPGA) is better here than C-to-Verilog. So in our case there is no automatic generator, code just helps you to avoid errors. Python program imports Verilog parameters/localparams (just constants and the the ones derived from them using expressions) and catches most of the typos when I write the generator code (not dramatically shorter than what it generates). This allows me to be flexible - the instantiated modules are not very uniform and not all have exactly the same interface - many were developed a long time ago starting as early as 2002. Not many are that old, but there are still many interface variations, and I do not mind going once more through them before switching to the C work from Verilog. I want just two things:

- reduce the number of possible errors as a result of the manual translation and

- make this (somewhat hand-crafted) converter be able to synchronize future changes in Verilog code to the C code that uses it, so five years from now it will be easy to add functionality to the system.

And thanks again for the links - I'll look more into your code.