Historical nit: I always considered the CDC 6600 to be the first commercial RISC machine, although given its strange architecture, I can see that others might disagree. It had multiple floating point and integer processors. An assembly programmer had to be aware of them all. I would not write two FP divides in a row because the second would stall waiting for the first to finish. I could write two consecutive FP multiplies, because there were two FP multipliers. Instruction timings were always a consideration in selecting registers, because you wouldnt want to try using a register that was the target of another instruction until that instruction had completed. Fortunately there were interlocks so that you would get the register contents expected rather than some undefined intermediate state. You always had two or three parallel instruction flows going to take ad vantage of as many of the 10 or so processors available.Other aspects of the architecture were truly strange. There were no load or store instructions. They were a side effect of setting an address register. I was the lead developer for two of the PL/I compilers for the 6600. Much fun. For those interested in strange architectures, I recommend the Wikipedia article https://en.wikipedia.org/wiki/CDC_6600.
Animats|9 years ago