Free Range VHDL – VHDL programming book available for free

[AlexanderDhoore]

I learned VHDL a few months ago. Since then I've build a few projects with it (some PCIe and ethernet stuff). I was very excited to learn a HDL because FPGAs seem like extremely powerful devices.

However, I now know why FPGAs aren't as popular as they could be: the tools are horrible. There is no way FPGAs will become popular among software developers unless the tooling improves dramatically. You can really tell that it was all build by hardware engineers who know their electronics very well, but not good software design.

[metaphor]

> There is no way FPGAs will become popular among software developers unless the tooling improves dramatically.

Care to expound in what way? I don't disagree with your opinion completely, but I suspect our reasons differ.

IMHO, the barrier isn't so much the tools, but a clashing of paradigms. All too often, traditional software developers without a solid foundational background in digital hardware architectures think they can easily pick up a HDL as if it were yet another programming language. The HD part is quickly forgotten as behavioral processes are hacked away using all too familiar constructs like if-then-else, for/while loops, etc. Inference warnings are ignored, timing constraints are shrugged off, metastability and synchronization aren't even a thing, let alone driver/receiver selection, pinmap planning, and signal integrity considerations at the PCB level...set to default and things should just work, right?

Anecdotally speaking, the only thing in common that HDLs have with traditional programming languages is a superficial charset. I think every software developer who has ever used tools like VS, Eclipse, Emacs, Vim, Make, Doxygen, Git, etc. would agree that each has its quirks and it takes a bit of use before a comfortable flow is discovered. FPGA vendor tools are no different, except--testbed simulations aside--there's that immutably distinct custom hardware integration end-game that most traditional software has the pleasure of conveniently abstracting away.

Any kernel/driver developers with HDL proficiency care to chime in?

P.S. ground-up PCIe/Ethernet FSM+datapath architectures after a few months without prior HDL experience is really impressive.

[sguav]

I feel the need to echo metaphor's reply. Even if tools for FPGAs do become better through the years, it doesn't mean they'll become "sw dev friendly".

If you do software you should be fluent with data structures, while on the FPGA/hardware side you "speak" metastability control and timing constraints. Just separate fields of interest.

When high level synthesis tools arise (such as Xilinx HLx, C -> straight to FPGA implementation) I still feel they are aiming the wrong audience: these tools still require a more-than-average knowledge of the FPGA fabric and implementation to work with, and that may be a good thing, but defies the HLS paradigm at its roots IMHO.

Source: humble experience through my job as an FPGA designer

[anfractuosity]

Cool! I'm going to attempt to learn VHDL, as I just picked up a Zybo board to learn with.

I'm just wondering what you used for PCIe out of interest? A while ago I picked up an Igloo2 board, but found their software impossible to use under Linux alas.

[lnsru]

There are many projects started some 10 years ago with Cyclone III FPGA and vendors do not want to scare the folks working with the same Quartus since then.

I wish I could simply synthesize my algorithms from C code instead writing that VHDL or Verilog code. SystemVerilog is a bit better, but the company does not allow using it.

[oelang]

We're 2017, VHDL 2008 was released 9 years ago, and this book is using VHDL 93.

[JoachimS]

VHDL compared to Verilog and SystemVerilog has much smaller user base and is less well supported by tools. And HW designers are hugely conservative when it comes to languages.

A raeson for this is that we have so many tools and the subset we can use the the GCD of all parsers in all tools.

Linter, EC-checker, simulator (at least one, often more than one), planner, synthesis/build tool, integration tool etc.

The synthesis subset of Verilog 2001 and 2005 are as far as I have seen accepted by virtually all tools. I tend to err on the side of caution and use Verilog 2001.

[metaphor]

As the old hardware commandment goes: if it ain't broke, don't fix it?

[EvgeniyZh]

You can always contribute, the link to github is provided in one of the comments.

[cyphar]

Quite a few people have been working on making VHDL more accessible by generating it all from Python. Tim Ansell gave a talk about it at LCA 2017 (https://www.youtube.com/watch?v=MkVX_mh5dOU), and it seems pretty cool.

[gluggymug]

No way to specify different clocks or resets from what I can see. That's a massive limitation to your designs.

[dang]

Discussed in 2012: https://news.ycombinator.com/item?id=3580537.

[EvgeniyZh]

Note that it was probably updated since then: Release: 1.18 Date: 8 March 2016

[notforgot]

Can I write an ASIC with it?

[bostand]

Yes you can!

(no idea why emddudley is claiming otherwise)

[kbumsik]

You can design an ASIC with HDL before it is produced but ASIC is not programmable. An ASIC is produced as it is. So you CAN'T WRITE an ASIC.

[blacksmythe]

See Introduction to ASIC Design for a detailed description:

  https://www.u-cursos.cl/ingenieria/2010/2/EL653/1/material_docente/bajar?id_material=305352

[emddudley]

No, because VHDL is used for configuring FPGAs. An ASIC is a different beast entirely.

[zump]

Please don't use VHDL. Use verilog, as a great cycle accurate FOSS simulator/compiler exists for it (Verilator).

[q3k]

While I also use Verilog, I don't understand your plea. VHDL has it's benefits over Verilog, most notably an actual type system (Verilog has none - you'll be redefining the same signal bundles over and over and over again). But yes, Verilator is quite nice.

I think both Verilog and VHDL are fairly terrible and are unnecessarily stuck at the connecting-wires-together paradigm. I have high hopes for systems like Clash[1]/Chisel[2]/SpinalHDL[3] to gain more widespread usage and finally make higher abstraction levels and metaprogramming standard in the industry.

[1] - http://www.clash-lang.org/

[2] - https://chisel.eecs.berkeley.edu/

[3] - https://github.com/SpinalHDL/SpinalHDL

[SoylentYellow]

Wow, that is some terrible advice. VHDL is just as valid a choice as Verilog. If a FOSS simulator is your requirement, VHDL has ghdl. Also, many companies only allow VHDL.

As better advice, it is worth writing something in both languages to get a feel which one you like better. Both have their own advantages and disadvantages (VHDL: Strongly typed, Verilog: Less verbose).

[analognoise]

This is not a good reason not to use VHDL- GHDL is open source and simulates VHDL?

Verilator is only useful if you don't need backannotated timing constraints.

[kevin_thibedeau]

> cycle accurate FOSS simulator

And how do you propose simulating asynchronous logic and delays? How do I back annotate synthesized net and cell delays into your one-true-simulator?

[pjmlp]

I rather use Ada like syntax.

[EvgeniyZh]

Any good Verilog/SystemVerilog book you can recommend?