[oelang]

The verbosity of VHDL isn't 2x it's more like 20% bigger on average and since VHDL 2008 it's pretty much the same. VHDL can be wordy but it also reads a lot easier & it looks more structured.

Verilog isn't C, it's C-ish, just different enough to make me make mistakes all the time like 'not' in verilog is '~' instead of '!', or the lack of overloading, the weird rules with signed & unsigned numbers and the implicit wire declarations etc. Verilog is full of surprises.

Do you like determinism? Have you ever tried running the same (System)Verilog design on multiple simulators? Almost every time you get different results, VHDL doesn't have this issue.

[rebootthesystem]

You seem to be taking this personally. What I described was my reasoning for choosing Verilog. It worked fine for me. I am not going to debate minutiae.

Also, who said Verilog is C? It feels like C but it isn't. It's simply a lot easier to context switch between C and Verilog than between C and VHDL. That's my opinion. You don't have to agree with it. There is no implicit obligation to agree with anything at all.

I have shipped millions of dollars in product very successfully using Verilog. Others have done so using VHDL. In the end it is a choice.

My intent was to give the OP one criteria he or she might be able to use in some way in making a similar choice.