And, please, it isn't code it is a Hardware Description Language. We all use "code" for short but let's not lose sight of what it is.
Many people come to FPGA design treating the thing as software. It isn't software. It's a hardware design and it is a hardware description language. Maybe it helps that my work in electrical engineering predates FPGA's and even PAL/PLA's. In other words, I spent years designing "raw" electronics.
When typing Verilog I think about circuits not software and I don't make a lot of mistakes because the circuits are designed on paper before typing code. Code is the hardware description, not the design environment.
I find that older hardware engineers are far better at this. Younger engineers treat it like software and go into this crazy type->debug->type->debug cycle that simply isn't the way you design hardware. Decades ago you had to know your shit. You couldn't throw a bunch of chips at a board and have to redesign it due to simple mistakes. Again, it ain't software.
So, no, I have no issues with Verilog debugging. I can't remember any serious debugging events in, say, twenty years.
What you are describing is just one aspect of programming with HDL that sounds similar to what one would do with a schematic editor. Fortunately, with HDL you can work at either a primitive level, or a more abstract behavioral level or anywhere in between. What if someone wants to design a library without knowing the specific device that will be targeted? You could use behavioral algorithmic style code using parameterized functions and lots of generate statements that could support multiple architectures. In that case there would be a lot of 'code' that does not have anything to do with the actual circuit but is still perfectly valid HDL. It is the software-like functionality of HDL that made schematic editors obsolete in my opinion.
rebootthesystem|8 years ago
And, please, it isn't code it is a Hardware Description Language. We all use "code" for short but let's not lose sight of what it is.
Many people come to FPGA design treating the thing as software. It isn't software. It's a hardware design and it is a hardware description language. Maybe it helps that my work in electrical engineering predates FPGA's and even PAL/PLA's. In other words, I spent years designing "raw" electronics.
When typing Verilog I think about circuits not software and I don't make a lot of mistakes because the circuits are designed on paper before typing code. Code is the hardware description, not the design environment.
I find that older hardware engineers are far better at this. Younger engineers treat it like software and go into this crazy type->debug->type->debug cycle that simply isn't the way you design hardware. Decades ago you had to know your shit. You couldn't throw a bunch of chips at a board and have to redesign it due to simple mistakes. Again, it ain't software.
So, no, I have no issues with Verilog debugging. I can't remember any serious debugging events in, say, twenty years.
odmkSeijin|8 years ago