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twtw | 7 years ago
>> Whether that would be worth it for instruction decoding, I don't know
There would be significant overhead to design a decoder such that it could switch between legacy and aarch64 only, but it could conceivably be done.
fyi clock gating isn't the same as power gating.
arghwhat|7 years ago
What you'd do then is to split the decoder into several blocks, so that there's a fan-out from a main decoder into the different sub-decoders, and then power down the sub-decoders. It's still entire blocks you power down.
Plus, I think the increased power consumption from this design (especially considering that the decoder now needs to stall on powered down sub-decoders) will outweigh the savings of powering down any sub-decoders.
> fyi clock gating isn't the same as power gating.
Of course not. Both clock gating and power gating are power saving designs. Clock gating and power gating both eliminate switching current entirely, while power gating also removes leakage current at the cost of larger architectural changes than those required by clock gating.
I'm out on a limb here, but I don't think power gating makes much sense outside extreme low-power devices.