[nominatronic]

"Vendors keep bitstream formats secret, so Verilog is as low in the abstraction hierarchy as you can go. The problem with Verilog as an ISA is that it is too far removed from the hardware."

I wonder if the author is aware that the bistream formats for both Lattice iCE40 series and Xilinx Virtex 7 series FPGAs have now been reverse engineered, and there is a complete open source toolchain that can be used for these. So Verilog is no longer as low as you can go.

Efforts of this type are also underway for other parts and there is a growing movement in this direction - see talks from Clifford Wolf at recent CCC events.

[typon]

Except these are not mainstream efforts supported by vendors.. Which means that they're effectively off limits to serious developers are large engineering firms who are the typical customers of FPGA hardware

[Aissen]

Yes, exactly like Linux, Apache, Docker or your favorite language were off-limits to serious developers in large engineering firms at some point in time. Things are evolving, so we'll see how it goes.

[ohazi]

Lattice is inching towards kinda sorta cheering them on, even though they won't openly admit it yet. They've been an underdog after Xilinx and Altera/Intel for a long time, but have gained a ton of popularity on hobbyist dev boards since Yosys showed up (search twitter for "tinyfpga" "icebreaker" "ecp5" etc. if you want examples).

The hobbyists playing with these boards at home are now more familiar with the parts and the tools, and there's also enough data comparing synthesis results between the open-source and proprietary tools with non-trivial designs that it's getting easier to predict performance (and be confident that the fitter won't crash).

Anecdotally, a lot of these hobbyists are now pushing to use Lattice parts at work, where appropriate.