[darsnack]

I just took a look at clash. HDL describes state in a very real way. Trying to represent stateful hardware using a functional language is just too complicated. I hate these toy examples of “look how easy an FIR filter is.” An FIR filter isn’t hard to write in Verilog to begin with. The real headache of Verilog is generate statements and multidimensional array indexing. And both of those problems are readily solved by System Verilog, System C, or any of the myriad of Verilog generators.

[rowanG077]

Your comment about clash and functional languages not handling state correctly are shortsighted. I have implemented real systems using Clash. The usability is simply leaps and bounds ahead of stuff like System Verilog and System C. The real headache of Verilog and the like is that it has little ability to abstract making you think that the real problem is stuff like multidimensional array indexing.

I'm not sure what you expect on a front page of a technology they have to show really simple toy examples and can't really dive in deeper. It's a front page... You can find myriad of more involved stuff if you would have googled for 5 seconds. For instance this https://clash-lang.org/blog/0001-matrix-multiplication/.

[darsnack]

I guess my point is that Clash is just a high level language that transpiles to Verilog. There a plenty of languages that already do this. So your original claim that it is a Verilog or VHDL replacement isn’t accurate. We still use Verilog.

Companies have been autogenerating Verilog from high level languages for decades.

[darsnack]

Just to be clear, I’m not trying to put down Clash. I disagree with your statement about it being an alternative to Verilog or VHDL. It’s like saying Java is dead because Scala exists.