Soviet tractor quality wasn't that bad, especially considering they shared a lot with tanks. And for the price they were likely even better :) . Not to mention that they came with capabilities to be repaired - something Intel in its chips will likely, and sadly, not include...
OOC, do you view Intel's projections as being too slow or just plain wrong (i.e., impossible)? I am not knowledgeable about this industry or the engineering behind it, just follow it casually, and I'm shocked to see 1.4nm on a slide.
are they? maybe if you push people really hard (completely unrealistic) they will still deliver much more than otherwise ("just" unrealistic). You might not land a rocket on Mars, but you can still land it on water...
I know that past performance does not indicate future results but looking at their 2013-2016 roadmap [1] which promises 10nm at Q1 2016 (which never happened!), I strongly doubt their future roadmap will hold.
And for the previous 40 years Intel was always about 1 year ahead of their competitors. I would never bet against Intel, that's been a losing game for far too long.
I don't think it's fair to say a leaked roadmap counts as Intel promising something, nor should 1 miss prediction immediately result in the dismissal of everything else. There's no pattern of Intel missing their roadmap to justify much suspicion. It's odd to put out something like this while 10nm's failures are hot in everyone's minds, but still.
At what point does this become securities fraud? How many retail investors are going to get annihilated when intel runs through their buy back authorization? This all feels like a ponzi scheme but with intel turning the crank using their own cash.
Woah there pal, you're forgetting that they spun up their 22nm process again in 2018 [1]. Intel has a lot of fab headaches right now. A reminder that 22nm debuted in 2011, and 14nm was 2014.
So if Intel actually stayed on track for this roadmap, they're saying "we only have 10 years left to advance our fabs". Unless 1.4nm is actually meaningless, they'd be edging up to electron tunneling issues with a contacted gate pitch of ~10 atoms across.
I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.
> "we only have 10 years left to advance our fabs"
Well, only 10 years left to advance with silicon wafers; once improvement truly becomes impossible there presumably we'll see even more resources go into trying to find practical replacements.
> It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law.
> Just don’t ask how much it’ll cost.
I once got an opportunity to ask something similar to an Apple executive during a presentation on their hardware capabilities (it was a university event).
He laughed and answered another part of my question.
A poorly held secret in the semi industry is that transistors have stopped scaling at around 30nm - the practical limit of 193nm litho.
What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.
Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.
From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.
So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
Just as an interesting aside does anyone have a list of weird engineering hacks used in these processes to get smaller and smaller transistor densities? There must be some very clever stuff to jam them in there and still be able to etch the lines.
The first part covers EUV, which is key to advanced nodes. Then it moves on to more futuristic and tentative techniques. But the EUV part is a nice introduction for non specialist, with pointers to dig if one is interested.
It quickly introduces the various hacks we do in order to get ~30nm features on silicon. But the talk is quite dated (early 2010's), but never ceases to amaze me. Semiconductors are indistinguishable from magic indeed.
There is this interesting talk by Jim Keller.
Talks about new approaches (different transistor tech, architecture, etc) to keep moores law going for another decade or so. You should defintely check it out if have time.
https://www.youtube.com/watch?v=oIG9ztQw2Gc
You can always count on Intel's marketing team for top notch slide presentations.
However, Intel is closer to 22nm than 7nm let alone anything smaller than that. ( I'm talking about consistent product lines that anyone can buy at a store ), not some Houdini show.
On the commercial side they have a huge footing and large tentacles so they don't need to worry too much about time-frames, let's hope they also don't worry too little..
Names with nm are just so called commercial names. They don't match from company to company.
Transistor density in millions of transistors per square millimeter is more relevant. For example: Intel 10nm is 101 MTr/mm², TSMC 7nm Mobile is 97 MTr/mm² so they are very similar.
Because "nm" doesn't mean nanometer anymore. Not in the context of CPUs anyway. Some time back, around the 34nm era, CPU components stopped getting materialy smaller.
Transistor count plateaued. Moore's law died.
To avoid upseting and confusing consumers with this new reality, chip makers agreed to stop delineating their chips by the size of their components, and to instead group them in to generations by the time that they where made.
Helpfully, in another move to avoid confusion, the chip makers devised a new naming convention, where each new generation uses "nm" naming as if Moore's law continued.
Say for example in 2004 you had chips with a 34nm NAND, and your next gen chips in 2006 are 32nm, then all you do is calculate what the smallest nm would have been if chip density doubled, and you use that size for marketing this generation. So you advertise 17nm instead of 32nm.
Using this new naming scheme also makes it super easy to get to 1.4nm and beyond. In fact, because it's decoupled from anything physical, you can even get to sub-plank scale, which would be impossible on the old scheme.
Edit: Some comments mention that transistor count and performance are still increasing. While that is technically true, I did the sums, the Intel P4 3.4Ghz came out 2004, if Moore's law continued, we would have 3482Ghz or 3.48 TERAHERTZ by now.
the "nm" doesn't mean what you think it means, since some time ago it's become unrelated to actual physical dimensions, and now it just means "a better process".
What kind material science improvement would make non-marketing, real ~10nm scales a reality? I literally have no idea how RnD works in this field. Is it trial and error? How do these scientists come up with ideas that increases the transistor density? Do our current gen CPUs have 2d or 3d curcuit layout? How one can learn about these stuff without working in the field?
A less than 10nm transistor with the same design transistors had 20 years ago does basically not work (you can do some analog hackery, but it's does not behave like a transistor).
Every semiconductor has a lower limit, for silicon it's ~10nm.
The biggest bottleneck is the laser (physics) used for etching of the layers ( and at some point, the number of electrons passing throught the gate, which intel solved using a "3D" gate.)
Adding to my previous post, a lot of people don't understand where 10nm EUV litho stands in the grand plan of thins.
"If EUV doesn't make a more performant chip, what it does?" EUV is there to alleviate extreme process costs associated with multiple patterning, and process cycle time.
Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology.
You have then lessen the amount of thermal processes performed on the device. You may have more defects, but on overall higher quality, higher performance devices in the end.
> Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021
Not to say it could never happen, but given how many years Intel has spent on 10nm with it always been 'next year' tech year after year, 7nm in 2021 seems overly optimistic for me.
I guess time will tell if they got it right this time.
The "backporting" doctrine clearly implies total lack of faith in process roadmaps, to the point of compromising processor designs and increasing cost and time to market to avoid committing to a millstone around the neck.
[+] [-] huffmsa|6 years ago|reply
They might ship 1.4nm, but it has a good chance of having Soviet tractor quality.
[+] [-] perceptronas|6 years ago|reply
[+] [-] avmich|6 years ago|reply
[+] [-] unixhero|6 years ago|reply
[+] [-] doyoulikeworms|6 years ago|reply
[+] [-] vsareto|6 years ago|reply
[+] [-] tomp|6 years ago|reply
[+] [-] marta_morena|6 years ago|reply
[+] [-] bjornjaja|6 years ago|reply
We need something new, not the same old “add more cameras to the phone” kind of innovations.
It’s the engineers that will make those discoveries—the investors can shove it. All they do is freeload on innovation and cramp peoples style.
[+] [-] soygul|6 years ago|reply
[1] https://wccftech.com/intel-processor-roadmap-leaked-10nm-can...
[+] [-] unknown|6 years ago|reply
[deleted]
[+] [-] bryanlarsen|6 years ago|reply
[+] [-] kllrnohj|6 years ago|reply
[+] [-] bob1029|6 years ago|reply
[+] [-] nightcracker|6 years ago|reply
[+] [-] eyegor|6 years ago|reply
[1] https://www.anandtech.com/show/13714/intel-adds-b365-chipset...
[+] [-] rrss|6 years ago|reply
[+] [-] huffmsa|6 years ago|reply
[+] [-] archontes|6 years ago|reply
[+] [-] eyegor|6 years ago|reply
I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.
[1] https://en.wikichip.org/wiki/intel/process
[+] [-] gsnedders|6 years ago|reply
Well, only 10 years left to advance with silicon wafers; once improvement truly becomes impossible there presumably we'll see even more resources go into trying to find practical replacements.
[+] [-] staticassertion|6 years ago|reply
[+] [-] Darvon|6 years ago|reply
[+] [-] wadkar|6 years ago|reply
> It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law.
> Just don’t ask how much it’ll cost.
I once got an opportunity to ask something similar to an Apple executive during a presentation on their hardware capabilities (it was a university event).
He laughed and answered another part of my question.
[+] [-] baybal2|6 years ago|reply
What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.
Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.
From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.
So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
[+] [-] andy_ppp|6 years ago|reply
[+] [-] yaantc|6 years ago|reply
The first part covers EUV, which is key to advanced nodes. Then it moves on to more futuristic and tentative techniques. But the EUV part is a nice introduction for non specialist, with pointers to dig if one is interested.
[+] [-] sl-1|6 years ago|reply
It quickly introduces the various hacks we do in order to get ~30nm features on silicon. But the talk is quite dated (early 2010's), but never ceases to amaze me. Semiconductors are indistinguishable from magic indeed.
[+] [-] aklascheema|6 years ago|reply
[+] [-] deepnotderp|6 years ago|reply
[+] [-] PedroBatista|6 years ago|reply
However, Intel is closer to 22nm than 7nm let alone anything smaller than that. ( I'm talking about consistent product lines that anyone can buy at a store ), not some Houdini show.
On the commercial side they have a huge footing and large tentacles so they don't need to worry too much about time-frames, let's hope they also don't worry too little..
[+] [-] kuu|6 years ago|reply
[+] [-] Nokinside|6 years ago|reply
Transistor density in millions of transistors per square millimeter is more relevant. For example: Intel 10nm is 101 MTr/mm², TSMC 7nm Mobile is 97 MTr/mm² so they are very similar.
[+] [-] fungicide|6 years ago|reply
Transistor count plateaued. Moore's law died.
To avoid upseting and confusing consumers with this new reality, chip makers agreed to stop delineating their chips by the size of their components, and to instead group them in to generations by the time that they where made.
Helpfully, in another move to avoid confusion, the chip makers devised a new naming convention, where each new generation uses "nm" naming as if Moore's law continued. Say for example in 2004 you had chips with a 34nm NAND, and your next gen chips in 2006 are 32nm, then all you do is calculate what the smallest nm would have been if chip density doubled, and you use that size for marketing this generation. So you advertise 17nm instead of 32nm.
Using this new naming scheme also makes it super easy to get to 1.4nm and beyond. In fact, because it's decoupled from anything physical, you can even get to sub-plank scale, which would be impossible on the old scheme.
Edit: Some comments mention that transistor count and performance are still increasing. While that is technically true, I did the sums, the Intel P4 3.4Ghz came out 2004, if Moore's law continued, we would have 3482Ghz or 3.48 TERAHERTZ by now.
[+] [-] riffraff|6 years ago|reply
EDIT: for something to read https://en.wikipedia.org/wiki/10_nanometer
[+] [-] nootropicat|6 years ago|reply
[+] [-] unknown|6 years ago|reply
[deleted]
[+] [-] diegoperini|6 years ago|reply
[+] [-] kristofferR|6 years ago|reply
https://www.youtube.com/watch?v=f0gMdGrVteI
[+] [-] brennanpeterson|6 years ago|reply
If.you are visual, Coventor has some nice visualizations. And I really like the work from Nikonov and Young.
If you really.want to get into the ideas, the series.of.papers and notes on E-tau scaling rules are great. Maybe not complete, but good.
Ideas for density aren't too hard: shrink pitch and fold into the z dimension. 3DNand is a folded NAND string, after all.
On materials, it really is driven by etch and lithography (collectively, patterning). Mostly not materials themselves.
[+] [-] marcosdumay|6 years ago|reply
Every semiconductor has a lower limit, for silicon it's ~10nm.
[+] [-] rusticpenn|6 years ago|reply
[+] [-] baybal2|6 years ago|reply
"If EUV doesn't make a more performant chip, what it does?" EUV is there to alleviate extreme process costs associated with multiple patterning, and process cycle time.
Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology.
You have then lessen the amount of thermal processes performed on the device. You may have more defects, but on overall higher quality, higher performance devices in the end.
[+] [-] josteink|6 years ago|reply
Not to say it could never happen, but given how many years Intel has spent on 10nm with it always been 'next year' tech year after year, 7nm in 2021 seems overly optimistic for me.
I guess time will tell if they got it right this time.
[+] [-] HelloNurse|6 years ago|reply
[+] [-] randyrand|6 years ago|reply
[+] [-] dmos62|6 years ago|reply
[+] [-] metalforever|6 years ago|reply
[+] [-] HocusLocus|6 years ago|reply
[+] [-] RosanaAnaDana|6 years ago|reply
Edit: oof with the down votes. Jesus people; comma added for clarity.