[ZirconiumX]

Could you please point [6] at https://github.com/nmigen/nmigen which is the new upstream after a hard fork?

Additionally, I'd like to clarify that nMigen generates Verilog indirectly; it actually generates RTLIL, which is the intermediate representation of Yosys, and then Yosys turns it into Verilog after some cleanup passes.

I'll happily admit to being biased, but nMigen is so much easier for me to work in than Verilog ever was.

[magicalhippo]

Ah, I saw the redirect but figured it was better to use the plain URL. Sadly too late for an edit now.

Hadn't quite gotten the connection with Yosys right yet, as I haven't yet started with nMigen, but yeah I definitely want to go there. But like I said, I prefer getting a good handle on Verilog first so I know what to look for when things go wrong.

I was inspired to all of this by the YouTube video series by Robert Baruch[1], where he tries to recreate the 6800 CPU on a FPGA using nMigen with formal verification.

[1]: https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPS...