[jxj]

Indeed, not only the viterbi but also many basic building blocks in the Xilinx and Analog Devices reference design which is the starting point of our openwifi project.

Viterbi won't be an issue, we know how to write our own viterbi decoder on FPGA. It just need some time.

A Thorough and comprehensive IP block analysis will be needed and we will also evaluate how big the effort will be to replace all (almost) the big company owned blocks. We have to do this analysis and invest effort in the future, because we really want to tape out a real opensource WiFi baseband chip! As the first step, RF won't be integrated.