Low-level details of the Zen 2 microarchitecture [pdf]

[davidtgoldblatt]

Of particular interest is section 20.18 -- "Mirroring memory operands"; extending (something like) register renaming to memory.

[boxfire]

I wonder what the limits are on that, and if it chains very deeply, e.g mreg ("memory register") to op to mreg to op to mreg.... What's the limit? Can this be used to extend the optimization of some chained computations via a kind of unrolling?

[phkahler]

A better name might be "Memory Operand Forwarding" since the data is probably coming from a write buffer.

[enchiridion]

Can anyone comment on how secure this architecture is against speculative execution attacks vs. Intel?

[Reelin]

I have a (likely silly) question for anyone well versed in low level CPU stuff. §20.7 says there's a stack engine that optimizes manipulation of the stack pointer. Does this only apply to the dedicated hardware register (ie %rsp) or to other registers as well?

(Potentially related, assuming it's of benefit are modern compilers smart enough to repurpose %rsp (is this even allowed?) if I use a block of memory as a stack inside a hot loop?)

[cepp]

Take this with 2 cents since I'm not versed explicitly in Zen architecture, but it's likely only the SP. Usage patterns are fairly easy to deduce at compile time and are optimized, i.e. loop tiling, thus I think it's fair to assume the optimizations are leveraged against this. For example, if you can predict the loop pattern you can repurpose the SP.

[foota]

Funny enough, I ctrl fed for an optimization problem I've been wondering about and found a couple mentions of it (branch vs conditional move)

[jordiburgos]

Could all these insights added to an Artificial Intelligence (AI)? Then the AI would find the best way to compile, re-arrange instructions, etc...

Just thinking...