Can someone ELI5 how TSMC is able to produce sub-7nm chips? I know quantum tunneling and the like becomes an issue at this size. I don't have a great physics background so I'm struggling to find a simple enough explanation for how they are dealing with this. Is it not as big a deal as I may think?
The number 7nm 5nm etc. ceased to refer anything physical after the technology moved on from planar transistors. Now it's just a commercial name for a generation.
The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.
They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).
der8auer recently did a 3 part video on YouTube where he cut up AMD and Intel chips and looked at the transistors with an electron microscope. It sheads some light on meaning (or non-meaning) of the node names. Is also really interesting;
The nm process numbers refer to the necessary dimensions of a theoretical planar transistor to achieve the same density as this process. Planar transistors haven't been used for at least a decade. To make matters worse there is no standardized planar transistor design so ultimately you cannot derive any meaning from these numbers other than as a fancy version number that tells you which process is newer. As many others have commented: It's much better to just look at overall transistor density.
FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.
Not the explanation you're looking for, but the CTO at TSMC co-invented the modern FinFET transistor. They've probably good a really good grasp on what issues block development of smaller features, and know how to find ways around those limits.
To make an analogy: I think a good way to think about it is that the 7nm node doesn't actually produce chips with 7nm features, it uses a "knife" (actually it's a lithography process) which is able to cut things as small as 7nm . That enables it to be more precise than a bigger "knife" so even though the size of the chip features is >7nm they are still able to be smaller than features cut with a 10nm "knife".
I don't actually know anything about chip production. But that's what I've picked up from HN.
for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."
https://www.youtube.com/watch?v=3otqUu-7WUQ
Surprising for the flashy marketing style of the video it really explained to me the difference between FINFET, GAA and MBCFET really well.
Is Samsung and IBM stronger in structural R&D then they are at FABs?
FWIW I thought Samsung trademarked the name MBCFET. Not saying that is in fact worth much, just that I know for a fact Samsung has been concrete about when this is going to be a process customers can use.
On paper I don't think it's risky to say everyone is looking at GAAFETs and MBCFETs, they're the evolution of finFETs (okay, we have the fin, what about more than one fin? Okay, how about the channel is surrounded by the gate (Gate-All-Around)?)
How far along is everyone to making them commercially available with good yields, ¯\_(ツ)_/¯.
I think the surprising thing to me was TSMC has thus far (as of like a month ago) been of the mind "nah, finFETs are fine". But keep in mind, that was for their 3nm node, which this isn't.
I think that Intel is one step behind. They'll likely produce 7nm in 2024 which should be comparable with TSMC 5nm. But TSMC 5nm already available for Apple.
It depends on a lot of factors, but mainly cost and yield.
Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help.
So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024.
Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )
With this news, how much of a lead do they have over Intel now? When is Intel realistically going to ship their next node? Or is it all still perpetually delayed with no end in sight?
[+] [-] jmt_|5 years ago|reply
[+] [-] Nokinside|5 years ago|reply
The most important dimensions are the gate pitch and metal pitch. For TSMC's 7nm process they are something like 60 and 40 nm and go down in the future to something like 30 nm and 20 nm in the 2nm process. Fin width might be the closest thing to commercial name.
They are not even comparable across companies. For example, TSMC 7nm process technology has 91 MTr/mm², Intel's 10 nm prosess technology has 100 MTr/mm². Samsung 10nm has 52 MTr/mm². (MTr/mm² refers to millions of transistors per mm²).
[+] [-] robert_dipaolo|5 years ago|reply
https://youtu.be/uEMDkbF3hu0 https://youtu.be/uXu_1zXOZdY https://youtu.be/_wAeL3f3iV4
[+] [-] imtringued|5 years ago|reply
FinFET and GAA (gate all around) are 3d transistor designs. Therefore you get impossible and purely theoretical planar numbers.
[+] [-] vkou|5 years ago|reply
That number has nearly zero bearing on the actual physical sizes of the chip's components.
The only people who know about the exact dimensions are the firms placing manufacturing contracts with TSMC.
[+] [-] 1000100_1000101|5 years ago|reply
https://spectrum.ieee.org/semiconductors/devices/how-the-fat...
[+] [-] nicoburns|5 years ago|reply
I don't actually know anything about chip production. But that's what I've picked up from HN.
[+] [-] rasz|5 years ago|reply
for reference "TESCAN is a leading global producer and supplier of scanning electron microscopes, focused ion beam scanning electron microscopes and micro-CT solutions."
[+] [-] tmd83|5 years ago|reply
Is Samsung and IBM stronger in structural R&D then they are at FABs?
[+] [-] LargoLasskhyfv|5 years ago|reply
[+] [-] throwaway4good|5 years ago|reply
What about Samsung or Intel? Or research labs that do smaller runs?
[+] [-] gimmeThaBeet|5 years ago|reply
On paper I don't think it's risky to say everyone is looking at GAAFETs and MBCFETs, they're the evolution of finFETs (okay, we have the fin, what about more than one fin? Okay, how about the channel is surrounded by the gate (Gate-All-Around)?) How far along is everyone to making them commercially available with good yields, ¯\_(ツ)_/¯.
I think the surprising thing to me was TSMC has thus far (as of like a month ago) been of the mind "nah, finFETs are fine". But keep in mind, that was for their 3nm node, which this isn't.
https://www.anandtech.com/show/16041/where-are-my-gaafets-ts...
[+] [-] vbezhenar|5 years ago|reply
[+] [-] j4nt4b|5 years ago|reply
[+] [-] ksec|5 years ago|reply
Example; Apple didn't use any 7nm EUV variant in A12/A13. While Huawei used it for their SoC. Having said that MBCFET, or more commonly known as GAA was originally scheduled for 3nm in 2022, so giving another 2 year to bake should help.
So yes, if everything were executed to absolute perfection, then we should see a 2nm Apple Silicon in 2024.
Note: While Wccftech has gotten a lot better in the recent 12 months or so, I still wouldn't put them into reliable and trusted source. It is good for rumours and entertainment, but that is about it. ( Personally I would rather not have it appear on HN )
[+] [-] vbezhenar|5 years ago|reply
[+] [-] Alopis|5 years ago|reply