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PeCaN | 5 years ago
So… what, it should take 5 instructions?
Executing more instructions for a (really) common operation doesn't mean an ISA is somehow better designed or "more RISC", it means it executes more instructions.
>And x86_64 CISC instructions devolve to a pile of microcode anyway.
Some people seem to have this impression that like every x86 instruction is implemented in microcode (very, very few of them are) and even charitably interpreting that as "decodes to multiple uops" (which is completely different) is still not right. The mov in the example is 1 uop.
tom_mellior|5 years ago
True. But as bonzini points out (or rather, hints at) in https://news.ycombinator.com/item?id=24958644, the really common operation for array indexing is inside a counted loop, and there the compiler will optimize the address computation and not shift-and-add on every iteration.
See https://gcc.godbolt.org/z/x5Mr66 for an example:
compiles to a four-instruction loop on x86-64 (if you convince GCC not to unroll the loop): and also to a four-instruction loop on RISC-V: This isn't a complete refutation of the author's point, but it does mitigate the impact somewhat.PeCaN|5 years ago
ncmncm|5 years ago
But hash tables are used here and there, also in loops.
Some people know them as "dictionaries" or "key/value stores".