[exged]

Reticle limited on Samsung 8nm means plenty of room is available on TSMC 5nm.

Also, GDDR does not have appreciably higher latencies than DDR memory when measured in nanoseconds. It's just more expensive than DDR and much more limited in terms of capacity.

If Apple does go the "huge SoC" route I'd expect to see HBM2 memory with socketed DDR4 or DDR5. It'd provide the best of both worlds - extremely high bandwidth and low latency for a small portion (say 32-64GB) of the memory, and high capacity for the rest (say 1-2TB), all without compromising the unified memory concept.

This is not without precedent - recent Xeon Phis, for all their other shortcomings, have had a similar memory hierarchy.

[modeless]

Yeah but when discrete GPUs get to 5nm they will still be reticle limited. They're not going to stop getting bigger. If Apple maintains a process node advantage maybe they could do SoCs to compete with discrete graphics at the previous node but I think Nvidia will catch up.

I agree that a combination of HBM and DDR sounds pretty good for a unified memory architecture. Are you imagining it as just another layer in the cache hierarchy or something actively managed?

[tinus_hn]

How is it a unified memory architecture if one part is faster than another? Sounds rather non-unified.

[modeless]

"Unified" in this case refers to the CPU and GPU having the same access to memory. This could still be true even if part of the memory is faster, as long as it's faster for both CPU and GPU.