Most fpgas are exactly mini async srams used as LUTs. The old MachXO series I'm working on actually allows using the luts as 16x2 bits RAMS (synchronous, single port or pseudo dual port). It also integrates a d flipflop/latch, a couple of muxes and some carry logic in each cell to give a little more power/flexibility, but the main architecture is sram luts, flipflops and giant muxes at each input to do the routing
loup-vaillant|4 years ago
Most fpgas contain mini async srams used as LUTs. It's very different from using one giant LUT, which is what abusing memory chips is all about.
The LUTs we find if FPGAs are very small, often with as little as 6 input bits. Because the size of the LUT grows exponentially with the number of inputs, there's a natural sweet spot: two few inputs, and the LUT isn't powerful enough. Too many, and the LUT is too bloated.
Using a 64K ROM to encode a 16-bit LUT definitely leans in towards "way too bloated" for me.
AndresNavarro|4 years ago