[mih]

You got it right. Translating from a logical design to a physical design requires following rules laid out by a foundry for a given process node (5nm, 7nm etc.). To check if a physical layout confirms to a node, Design Rule Checking [1] is performed as part of the Physical Verification step in EDA [2]. The simulation/checking is highly complex and takes hours (sometimes days) even with sufficient parallelization. Once a design passes the checks, it is deemed ready for manufacture by the foundry.

[1] https://en.wikipedia.org/wiki/Design_rule_checking

[2] https://en.wikipedia.org/wiki/Electronic_design_automation#A...

[x0x0]

ty!