Mixed instruction set schedulers? Intel 12th gen issues

[doommius]

I've been looking a bit at the news recently about the intel 12th gen CPUs, and how they disable the AVX-512 instruction set if the efficiency cores are enabled. which seemed like a weird and poor implementation that bottlenecks some workloads and leaves quite a bit on the table in terms of performance. Why isn't this handled in the scheduler ? all the major operating systems already support the big/small core design. Why isn't the instruction set requirements simply passed to the scheduler via program headers to dynamically schedule tasks in the most efficient/fastest manner?

I read a bit up on the topics and there is already research into the topics. so I wonder why the approach intel used is even there. http://web.cs.ucla.edu/~tjn/papers/pact2018-hybrid-sched.pdf

Why isn't a better solution used? and why just disable the functionally as it seems like low hanging performance gains from intels side? And isn't this a approach to also look into more as modern hardware utilize ASIC style or dedicated hardware for more operations and will so going forward?

[ayende]

There is no facility to say "this program runs AVX512 instructions". For that matter, a program may not know that it does. If it uses a JIT, loads a dynamic library, etc.

And if you mess it up, you get an invalid instruction, so that is something that you really want to avoid.

[ant6n]

The invalid instruction can be caught by the kernel, which can inspect the instruction, see that it's avx512, mark the process as avx enabled, and only run it on p cores.

Some sort of settings or policy could be set up so that processes don't force themselves onto the p cores.

[doommius]

Agreed, but there has to be a better solution then just outright disabling the features.