[boibombeiro]

The comparison of power usage is often done in the context of external memory. When talking about in-chip memory it becames an apples to orange comparison.

For start, it doesn't make sense to power gate a SRAM. So they are always leaking power. And despite writes not being common, reads are. Most application with SRAM reads all the metadata in parallel looking for a match (and often the data too due timing constraints and increased size of control logic because the extra complexity). And reading uses power.