[jalopy]

Also with their packaging tech (EMiB and Foveros) they can mix and match chips from different fabs - ie, combine P-cores from TSMC fabs with E-cores from their own (possibly older) fabs. Alder Lake is the first real stab at the "chiplet" architecture, and it seems to be a very good outing. Future iterations will only improve, and at Intel's purchase scale economics they'll be able to manufacture chiplet designs that match market needs for the highest margin or pricing pressure to squeeze competitors, if needed.