[sabhiram]

We run a cluster of RISC-V CPUs based on open source designs to schedule and post process workloads for our edge accelerator ASIC.

10/10 would do it again, except this time we may pay SiFive or someone like that for something requiring less "customization".

[marktangotango]

Interesting, can you say anything about what sort of chip to chip communication is used? AXI, Wishbone, plain old serial?

[sabhiram]

AXI primarily.

But, I should also mention, we only use the RISC-V cores as a pre/post-processor, scheduling engine, service processor. We have custom hardware that does the bulk of the inference math (we are a convolutional accelerator with a number of constraints traded off for speed and power). The fabric itself is driven by engines that are programmed by the scheduling engine (RISC-V).

Happy to answer more specific DMs.