[tsmi]

> The main point of verilog is to simulate digital logic

I disagree. A HDL, which verilog is an instance of, provides a precise description of a digital machine.

Once you have that description, many things can be done with it. For example you can simulate the machine which is to be produced.

The problem is HDL looks like an algorithm, because it is. But it’s not a precise description of a computation, it’s a description of an object.

Most people who I’ve observed program verilog badly do so because they confuse the two. Kinda like confusing giving directions with giving instructions to make a map. Directions and maps are highly related, but they’re not the same thing.