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john567 | 3 years ago

This thing branched horribly. You had to use instructions to selectively write to distinct memory locations to avoid typical branching because misprediction was expensive.

This was Frostbite/Battlefield 3 era. Good Times.

discuss

order

bluedino|3 years ago

Is that a POWER thing or what was the main cause?

corysama|3 years ago

On top of being power architecture, both the 360 and the PS3 chose to push the 4 GHz clock limit before everyone else. To do this they sacrificed lots of speculative and out of order execution features of the CPU. The thinking of the hardware engineers was that the software is compiled for a fixed architecture doing a fixed job so the compiler should be able to statically order the instructions to make the best use of the very long, very static, very linear pipeline of the CPU. In practice, that only makes sense for very long stretches of instructions with no branches and no cache misses —which is completely the opposite of every piece of gameplay code ever written. The CPUs were great at large scale linear algebra. Not great at much else.

zenron|3 years ago

As said in other comments, not a power thing. Example, the Nintendo Wii U chose to use 3 1.2ghz (iirc) Out of Order execution cpu's that were more like a PC than the cores in the Xbox 360 even though sounding similar in instruction set and composition.

This lead the Wii U to be able to do things like Run Mass Effect 3 and Deus Ex better (arguably) than the PS3 and 360 most of the time. The Wii U was probably the better hardware platform in hindsight but it came too late and the development tools were not as robust so ports just kinda afterthoughts.

Veliladon|3 years ago

It wasn't a POWER thing since POWER has been superscalar since the 604 back in '94. This was because when you're designing for a console and paying by the wafer instead of shopping around for a pre-finished unit one needs to consider die area more strictly. Something had to give in the design and given MS controlled the design of the whole stack they thought they could do parallelism at the thread level in the OS scheduler rather than having to devote massive amounts of die area to it.

monocasa|3 years ago

The xenon core was a slightly modified cell ppe, where there it was focused on saving gates for the cores needed for system management versus more spus.

The idea using it in xenon without the spus was that high perf code could be tailored specifically for this core's uarch being a console, so the in order nature wasn't the worst thing and the gate savings are pretty huge.