[Corazoor]

Depending on the clock frequency of the chip, a change in the length of signal carrying lines (i.e. from one gate to the next) can already result in a phase/timing shift that ruins the circuit. It is not uncommon to have data lanes that are longer than necessary, just to keep signals on different lines in sync.

Even if you ignore all the other complications when switching nodes (and there are a LOT!), this alone prevents simple downscaling of circuits. It is very likely that after downscaling at least part of the interconnects have to be rerouted.

As for automation of that task: It's the traveling salesman problem in disguise. Which means that you CAN automate it, and there exists software for that purpose, but the result are hardly optimal, and most likely leave quite a lot of possible performance on the table.

Add to that all the other necessary changes when switching nodes, and it becomes fairly obvious that switching nodes, even if only porting 1:1, is a massive effort that can easily span YEARS.