[Rarebox]

This would make sense right? You probably can't run all cores at max turbo frequency before hitting power and thermal limits. So dividing chiplets based on binning would result in good performance for 1-8 -threaded tasks while reducing chip lottery.

(But it's possible there are other reasons for the discrepancy)

[formerly_proven]

The first CCD is binned for the SKU's spec, the other is whatever. This has been true for all chiplet Ryzens. Though the effect used to be more extreme, I had for example a 3900X where the second CCD only managed to run at 4.1 GHz under load, compared to ~4.4 GHz on the first CCD (and 4.6 GHz being printed on the box). That's pretty common with those.

[xattt]

Is there optimization being done by AMD to locate the best performing chiplet on the best possible place on the bus?

[wmf]

There's no bus and thus no place on the bus.