[tspiteri]

> 4 NANDs and an inverter give you a D-latch that lets you synchronize your circuits to the clock signal.

A D latch would be enabled all the time the clock signal is high, so it is not suitable for synchronizing your circuits to the clock signal. What you need is for the device to store the input at the instant when the clock signal goes from low to high. (Using the tech terminology: the 4-NAND D-latch has level triggering, while for the clock you want edge triggering.)

[bcrl]

You can build an edge triggered flip flop from just NAND gates. Real world gates have delay, which means that you can generate the enable signal by using a NAND gate to invert the clock and generate a pulse on the edge of the clock by ANDing that with the clock.