Notch's Specification for the In-Game DCPU-16

[unwind]

Just waiting for the first post about programming this CPU to pop up on Stack Overflow ... :)

It's quite an interesting architecture. From an initial perusal, I found these features note-worthy:

* Explicit access to PC as a register, makes "computed goto" trivial and very natural.

* Because of the above, there is no JMP instruction.

* Treating operations on registers as "values" makes the instruction set very orthogonal.

* No instructions for bit-manipulation.

* Lots of possible NOP instructions, like "SET PC,PC" (which I think should work, depends a bit on exactly when it's incremented but it looks safe).

* Word-addressed memory will make string processing interesting to implement. Maybe in space, everyone uses UTF-16.

* Single 64 K address space will put quite the limit on the amount of code, I guess the game will show how much code is needed to do anything.

* No I/O instructions means I/O must be memory-mapped, further reducing the space available for code. Maybe there will be bank-switching?

* No interrupts.

[keenerd]

> No instructions for bit-manipulation.

What? Plenty of opcodes for that. SHL, SHR, AND, BOR, XOR are all bitwise operators.

Unless you mean bitset and bitclear macros, but no self respecting embedded programmer uses those. I've disagreed with almost everything else Notch has done, but from a simple pedagogical standpoint, he's doing the right thing by leaving those out.

[wagabond]

I'm a self-taught programmer, and don't know much about CPUs. Would someone mind putting this into relatively plain english, I'm quite curious to know the practical implications of this. Can we expect to see Python running on it in the near future for example :) ?

[sp332]

> No I/O instructions means I/O must be memory-mapped, further reducing the space available for code.

In a tweet, notch said It's going to be dynamic later on, but right now [the keyboard is] a cyclic 16 letter buffer at 0x9000. 0=no char yet. Set to 0 after read. http://pastebin.com/raw.php?i=aJSkRMyC

[dspillett]

The thing that looked odd to me was:

>* IFE, IFN, IFG, IFB take 2 cycles, plus the cost of a and b, plus 1 if the test fails*

It is a long time since I worked in assembly, but I don't remember comparison functions having different timings depending on results when I were a lad.

(FYI, most of the assembler I played with was for 6502s (in the old beebs) with a little for the Z80 family and early x86)

[stephencanon]

Ask and ye shall receive: http://stackoverflow.com/questions/10012522/are-the-i-and-j-...

[stusmith1977]

> Explicit access to PC as a register, makes "computed goto" trivial and very natural.

Am I right in thinking ARM uses this model? I haven't worked on them since ARM2, but I have a hazy recollection...

[TomFrost]

> * Word-addressed memory will make string processing interesting to implement. Maybe in space, everyone uses UTF-16.

Everyone in Minecraft, too -- almost. The string encoding in Minecraft's protocol spec is UCS-2, just a sneeze away from UTF-16. It seems Notch has a soft-spot for large encodings. It makes sense from a calculation and lookup perspective, but I wonder if the increased bandwidth and storage of 16-bit blocks has a measurable impact.

[tptacek]

The DEC Alpha didn't have byte addressing either.

[zoul]

http://stackoverflow.com/questions/tagged/dcpu-16

[nknight]

With cleverness, I could see the memory constraints being not so terribly constraining, even without a (real) bank switching mechanism.

The reason we use "RAM" as we generally think of it is basically that other forms of storage are obscenely slow, right? In this case, however, our "mass storage" device would actually be... RAM. Just not directly-addressable RAM. Loading code and data from "disk" as-needed could be relatively fast.

Edit:

> No interrupts.

Good catch, that's probably something we'll see added. I don't think Notch will like emulating a thousand polling CPUs...

Edit 2:

Just spotted this in Notch's twitter feed: https://twitter.com/#!/notch/status/187454444571598848

"An emulator is coming Eventually(tm). I want to sort out some more IO design first, not release too early."

So, I/O is still up in the air.

[phoboslab]

Now here's an interesting bit:

"Question: can we trade the programs we create? How will you stop malicious viruses etc?"

"yes. And I won't stop viruses, the players will have to do that themselves."

~ https://twitter.com/#!/notch/status/187474819980328962

[jiggy2011]

I worry about the griefing potential here.

I can imagine nothing pissing off a noob more than getting a virus within 10 minutes of play and having no idea how to stop his ship from self destructing.

Perhaps this will need some sort of firewall system built in where ships cannot communicate unless ports have been explicitly opened. Perhaps some sort of communications proxy that can serve for safe communications.

It could have a system similar to EVE where high security systems have infrastructural to mitigate risk whereas low sec systems lack this but contain the best rewards.

[exch]

Nice. With a bit of fiddling one could perhaps invert an enemy's shield polarity. That always seems to work miracles in any sci-fi show.

[andypants]

Somebody can write anti-virus software for the game and sell it!

[jonnycowboy]

This is covered fairly extensively in Neil Stephenson's Snow Crash. It even uses the same term for the persistent world "metaverse!"

[Florin_Andrei]

Notch is playing God.

Well, actually that sounds like a recurring theme, now only taken to a more complex extent.

[nooop]

He won't stop viruses, but will those viruses be made illegal in UE?

[SideburnsOfDoom]

Context:

For those who are puzzled (as I was) as to what this CPU is for, I found this:

> Notch's next game, 0x10c, "will allow players to create their own spaceship in the far, far future of an alternate universe ... More exciting - especially for those versed in programming languages - is the ship's computer. It's a fully-functional 16-Bit CPU that controls the entire vessel..." http://www.dealspwn.com/notchs-space-trading-game-real-calle...

Also: http://www.theverge.com/2012/4/4/2924594/minecraft-creator-n...

http://0x10c.com/

[stephengillie]

It's good to see Notch working on the Little Coder problem, even if that's not his direct intention. :)

[xer0x]

Thanks for mentioning this. I was getting real confused about why someone would create a CPU/ASM for their game. Thought he'd then have to build the new game on top of that CPU and notch is crazy but that seemed a bit much..

[evilpie]

Just for fun, I wrote a disassembler for his instruction set. https://gist.github.com/2300590

I previously wrote some assembler routines for x86, which is very complex, working with Notch's design is a breeze and actually enjoyable.

Does he somewhere mention if the code is loaded into the RAM? This would make self-modifiable code possible.

[evincarofautumn]

It doesn’t say in the spec, unless you interpret the memory dump for his assembled example as residing at address 0x0000 rather than offset 0x0000. But I don’t see any reason why PC shouldn’t refer to a RAM address. It would be great for code economy in such a constrained system.

[SimHacker]

Can't wait to see FORTH running on this CPU!

FORTH ?KNOW IF HONK ELSE FORTH LEARN THEN

[tvorryn]

That's my plan actually. It should be a lot easier to get going than C or an LLVM backend as others are suggesting.

[acron0]

I will admit, I used to think Notch was just a regular-joe programmer who had gotten extremely lucky with his strain of adventure game.

Now I know I was dead wrong.

[Ralith]

Emulating a very simple computer like this isn't hard at all; it's basically just a big array for memory, a few variables for registers, and a switch statement for instruction handling.

[tchock]

I am just in awe. This guy has the guts to imagine shit like this and pull it off.

[davedx]

I guess we'll be able to write our own malware to take over other peoples' ships, then? Pretty awesome, just call me Locutus :)

[gnarbarian]

the borg vs the binars.

[DanBC]

This might be a stupid question but where does the output go? Is it just a memory location? And does that memory location map to a "ship function"?

So, er, on a PC if I write data to address 0x378 it'll appear on LPT1. What's the equivalent on DCPU-16? If I write data to a certain address it'll appear on the missile bay ports?

Or is there a level of abstraction?

[a-priori]

If I had to guess, he's going to implement memory-mapped I/O. So, there's going to be another specification that lists various memory locations' functions. Reading from some will return information about the ship's systems; writing to other locations will control the ship.

[nightpool]

I/O is still being developed: https://twitter.com/#!/notch/status/187454444571598848

[rcamera]

For those interested, there is a C based implementation of Notch's DCPU-16 in github: https://github.com/swetland/dcpu16

I haven't tested it much, but it seems to work pretty well.

[overshard]

I wonder if it's just me but this game has me more excited about programming in ASM than I ever have, ever...

Also in this game I feel like I'll be playing the reverse role I play in real life. IRL I generally always advocate using things like Python and open sourcing everything. In this game I'm definitely going to pull a Steve Jobs, hire out a few friends of mine to program my ASM apps and sell them in some kind of Market for insanely marked up prices telling people that my Orange(TM) software is so much better than Macrosofts(TM)! (And it will be!)

[redthrowaway]

When you sell it, however, you'll be selling the source. No pre-compiled binaries, here. Might be a bit difficult to charge for something people can trade for free.

[clavalle]

I created a subreddit for this interesting aspect of 0x10c if anyone is interested:

http://www.reddit.com/r/dcpu_16_programming/

[sp332]

Here's some work (not mine) on a third-party implementation in Go :) https://github.com/kballard/dcpu.go/tree/master/dcpu

[ekosz]

I'm not a low level programmer, but could someone tell me if you could write a LLVM backend for this CPU? If one does that, could it not then work with many programming languages that support LLVM?

http://llvm.org/docs/WritingAnLLVMBackend.html

[cobbal]

I've never written an LLVM backend, but one difficulty that immediately jumps out at me is the 16-bit architecture.

LLVM specifies types with bitwidths and 32 is most commonly used, meaning a backend would have to either emulate 32 bits, forbid the frontends from generating 32 bits, or silently cast them all down to 16 bits.

[zoul]

https://github.com/krasin/llvm-dcpu16/

[Symmetry]

I've been tempted to learn Verilog, looks like I might have a fun project to start here, trying to pipeline this. If I were writing the instruction set I'd be tempted to put all the value codes for next word or PC next to each other so it would be easier to figure out at decode state if the PC would be doing anything wonky, but that isn't a huge impediment or anything. The instruction boundary problem with regards to going super scalar looks as bad as it is in x86, but that's straying pretty far from the design goals.

[duaneb]

I'd be interested to see details on memory protection. Self-modifying code means evolutionary programming, which I am very much for.

Conditional branching is strange.

[Florin_Andrei]

I'm guessing someone is already working on a real-world version of it in an FPGA. Just for fun.

[uvdiv]

I'm not sure if it's well-specified. What does this do?

    JSR POP

Does the argument POP (or [SP++]) get evaluated before, or after, the "[--SP] <- PC" implicit in JSR?

[rg0ne]

That compulses me to take Compiler class next semester, and write a C compiler for this precious fictional CPU.

And what about creating this cpu?

[JEBailey]

I follow most of what's occurring within this document, but there's a bit that's throwing me and I hope someone can shed some light. When you're processing the step

SET A,B

Does A have to represent a register, or is it a memory location or is it both and the registry is just a location in ram?

[viraptor]

a and b are just decoded value bits. That means they can be either one of those things. 0x00-0x07: registers themselves, 0x08-0x0f: addressing via register, etc.

[lukesd]

Hey guys. If you're interesting in discussing this, head on over to #0x10c-dev on Freenode!