The two dominate EDA companies are Cadence and Synopsys. All of the digital design tools for synthesis, place and route, and static timing analysis use the Tcl language as the built in scripting language. These tools have literally thousands of built in commands.
You can look up some of the tools like Cadence Innovus that I use every day. A single license has a list price of over $1 million. We get big discounts because we have about 800 licenses.
https://www.cadence.com/en_US/home/tools/digital-design-and-...
Then you write more Tcl code to script things within the tool. A standard thing is building a power grid. You need to write a for loop to build a metal 1 stripe every 5 microns. That's done in Tcl.
You have a list of clocks you need to define with names and frequencies. Use a Tcl array and a for loop.
Our CAD flow is literally tens of thousands of lines of Tcl code to take Verilog and go through all the steps until we get a GDS file with mask data to manufacture.
The confusion here stems from an acronym collision between Exploratory Data Analysis (where R and related packages like ggplot are popular) and Electronic Design Automation.
The "ecosystem" would just be, e.g. the suite of ASIC place and route tools, or FPGA synthesis tools, provided by each company. They pretty much all have TCL built in, for to help script them all together.
Each individual script is typically very ad-hoc, to address a specific shortcoming in a tool, or to get a particular mix-and-match of tools from various vendors integrated into a design pipeline.
That being said, it is an ancient and venerable tradition, dating back to the creation of tcl itself, and as long as we're making chip from Silicon it will be the duct tape holding it all together.
Not really. Most of the tcl that gets written is very straightforward and business-logic. The framework you're using is pretty much just the host tool. Trying to integrate other libraries is often difficult if the tcl runtime is missing some features (looking at you, xilinx...)
There really isn't an ecosystem. It's mostly just used for driving the tools and describing the configuration. For example, if you needed to generate power straps for an ASIC, you'd add a line to your place-and-route tcl script to generate them.
lizknope|2 years ago
The two dominate EDA companies are Cadence and Synopsys. All of the digital design tools for synthesis, place and route, and static timing analysis use the Tcl language as the built in scripting language. These tools have literally thousands of built in commands.
You can look up some of the tools like Cadence Innovus that I use every day. A single license has a list price of over $1 million. We get big discounts because we have about 800 licenses.
https://www.cadence.com/en_US/home/tools/digital-design-and-... Then you write more Tcl code to script things within the tool. A standard thing is building a power grid. You need to write a for loop to build a metal 1 stripe every 5 microns. That's done in Tcl.
You have a list of clocks you need to define with names and frequencies. Use a Tcl array and a for loop.
Our CAD flow is literally tens of thousands of lines of Tcl code to take Verilog and go through all the steps until we get a GDS file with mask data to manufacture.
maxbond|2 years ago
rhelz|2 years ago
Each individual script is typically very ad-hoc, to address a specific shortcoming in a tool, or to get a particular mix-and-match of tools from various vendors integrated into a design pipeline.
That being said, it is an ancient and venerable tradition, dating back to the creation of tcl itself, and as long as we're making chip from Silicon it will be the duct tape holding it all together.
tn1|2 years ago
inomenic|2 years ago
sweetjuly|2 years ago