[NextHendrix]

Software engineers can sometimes find it difficult as with a HDL you (should) describe hardware that exhibits the intended behaviour, rather than just directly describing the behaviour.

HDLs have familiar syntax that makes it seem like you can just program algorithms imperatively (for loops, if statements, functions etc) but it's all just a mean trick to catch software people out, and generally won't give the results you expect.

On top there's then the fact everything happens at the same time, the faff of making everything synchronised and making sure it meets timing and fighting the frankly awful tooling every step of the way.

Once you get it, it's fine, but you have to unlearn a lot of software muscle memory and keep the actual design work (boxes and lines) almost entirely separate from the implementation (typing your boxes and lines into a text editor).

[IshKebab]

I've written software for decades and didn't find it very difficult at all to pick up HDLs conceptually. The idea that you're writing a circuit that all executes in parallel is really not a difficult one.

The biggest issues are really:

1. The tooling is generally awful. Open source tooling is very primitive and not usable. Commercial tooling is unaffordable to hobbyists. There are a couple of exceptions:

a) Vivado which I haven't used extensively but seems fairly nice. Unfortunately the FPGAs it works with are not cheap.

b) I discovered that Intel provides a free version of ModelSim. I've used Questa a lot (the "pro" version of ModelSim more or less; their branding is confusing) and it's great.

It also doesn't help that all the tools use TCL which is also awful.

2. SystemVerilog is just a really bad, ancient language. It wasn't even designed for synthesising ASICs, let alone FPGAs! You're writing a simulation of an ASIC, and then some other tool tries to infer how it should run that simulation on an FPGA. It's a completely bonkers system.

It's not just the system that is bonkers. The language is too. Implicit casts all over the place, undefined values as part of the language (though not in Verilator!), multiple assignment types, ridiculously flexible array indexing.

Maybe VHDL is better... but unfortunately SystemVerilog won the language war in the ASIC space so that's what I know.

It also doesn't seem like we'll get a replacement any time soon. You'd need buy-in from the big vendors otherwise debugging will always be a total nightmare.

Though it would be nice if there was something like Typescript for SystemVerilog - something that fixed all the very rough edges and footguns but didn't change the code so much that debugging is painful.

[proto_lambda]

> Open source tooling is very primitive and not usable

Maybe you're working off old information, but the FOSS tooling (ghdl, yosys, nextpnr) is completely sufficient for hobbyists. If you're doing huge, high-speed designs on expensive FPGAs, sure, use the vendor tools, but for your average iCE40/ECP5-scale design, FOSS is the way to go.