[kiwidrew]

The 8088 has a four-byte instruction queue, and at times when the data bus would otherwise be idle the bus interface unit will prefetch the next instruction byte. So fetch and decode/execute are already overlapped.

What really slows down the 8088 is that each 8-bit transfer on the data bus requires four clock cycles. That means simply fetching the two-byte instruction requires eight clocks! Instruction fetch is so slow on the 8088 that it's virtually impossible to achieve the published instruction timing.

[codedokode]

Interesting, if I remember correctly, 8080 also required 4 clock cycles to fetch and execute a single-byte instruction. Did 8088 inherit some schematics from 8080? And 6502 uses 1 clock cycle for one memory access.