[ninjha]

I think Chisel's main win is that it is great from an open-source research perspective.

Taking advantage of the functional nature of Chisel enables a set of generators called Chipyard [0] for things like cores, networking peripherals, neural network accelerators, etc. If you're focusing on exploring the design space of one particular accelerator and don't care too much about the rest of the chip, you can easily get a customized version of the RTL for the rest of your chip. Chisel handles connecting up all the components of the chip. All the research projects in the lab benefit from code changes to the generators.

Chisel even enables undergraduate students (like me!) to tape out a chip on a modern-ish process node in just a semester, letting Chisel significantly reduce the RTL we have to write. Most of the remaining time is spent working on the physical design process.

[0]: https://github.com/ucb-bar/chipyard

[1]: https://classes.berkeley.edu/content/2023-Spring-ELENG-194-0...

[BooneJS]

Awesome! When I was an undergraduate all I could tape out was a small wafer of capacitors and correlate theoretical vs silicon.

Chisel is no doubt a developer velocity booster. And generating those components does help speed you along especially when they’re silicon proven.

But I’d wager that most industry silicon has a competitive edge to pay off the NRE, something bleeding edge that can’t get away from verilog interop.