[bippingchip]

These gate and metal pitch numbers don’t tell the whole story. In the end it’s logic gate density that counts.

And while decreasing the gate and metal pitch, also the logic gates have shrunk to be smaller (typically expressed by measuring the height of a gate in amount of metal tracks) from 9tracks down to 6tracks.

Changing the transistor from planar to fins, and now hopefully to ribbons with eventually stacked pmos and nmos are a big enabler.

That said, we’re still not hitting the ideal scaling numbers. We’re just doing somewhat better than what’s suggested by poly and metal pitch only.