> A barrier instruction forces all memory operations before it to complete before any memory operation after it can begin. That is, a barrier instruction effectively reinstates sequential consistency at a particular point in program execution.
> Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they can cost hundreds of cycles.
I may be wrong, but I think to readers who do not already know what barriers do and are, this makes barriers seem like blocking behaviours.
Barriers can induce blocking behavior though. A store barrier followed by a store operation can result in a blocking operation until the store buffer is flushed, and similarly for a load barrier.
Just to clarify your comment via a question: are you pointing out that barrier instructions are a scheduling ‘issue’ that the processor uses to order instructions versus something like a memory read that actually requires a pause in the execution of instructions?
The usual way that barriers were implemented was to simply stall the CPU pipeline. So yes, they do indeed have blocking semantics. IIRC mfence still does stall the pipeline on x86, but I think the CPU is a bit smarter for locked instructions.
I'm about to move into ARM development for a new-ish AI accelerator. Until now, I've mostly developed for x86.
In preparation for this, I've been reading up on ARM's looser memory consistency model, and C++'s rules regarding this. It's been pretty eye-opening.
I'm looking forward to seeing how much that ARM codebase takes advantage of the weaker guarantees that ARM permits. It seems like a trade-off of scalability vs. correct-code complexity.
[+] [-] liblfds-temp|1 year ago|reply
> Of course, this is exactly the behavior we were trying to avoid by introducing store buffers and other optimizations. Barriers are an escape hatch to be used sparingly: they can cost hundreds of cycles.
I may be wrong, but I think to readers who do not already know what barriers do and are, this makes barriers seem like blocking behaviours.
[+] [-] Maxatar|1 year ago|reply
[+] [-] throwaway17_17|1 year ago|reply
[+] [-] gpderetta|1 year ago|reply
[+] [-] CoastalCoder|1 year ago|reply
In preparation for this, I've been reading up on ARM's looser memory consistency model, and C++'s rules regarding this. It's been pretty eye-opening.
I'm looking forward to seeing how much that ARM codebase takes advantage of the weaker guarantees that ARM permits. It seems like a trade-off of scalability vs. correct-code complexity.
[+] [-] anonymousDan|1 year ago|reply
[+] [-] signa11|1 year ago|reply
it seems to be coming up kinda 404 for me. thank you !
[+] [-] sdbbp|1 year ago|reply
[+] [-] sdbbp|1 year ago|reply