[avianes]

Modern chip designs have an enormous amount of logic and therefore standard-cells. And when you are dealing with a huge amount of cell all together, it quickly becomes unmanageable, syntheses tools runtime explode, quality of results declines, results become chaotic, ..

So chip designs are spliced into partitions. Each partition is a part of your design that you synthesized separately. For example you may setup a partition for the core, and you can instantiate it multiple time into a core_cluster partition.

Note that: synthetiser's logical optimizer cannot work on logic across partitions, so you don't want to small partitions (otherwise you will have more manual optimize to do) but you also don't want too big partitions (otherwise runtime and development iteration time increase).

The question is what the good size for a partition ?

* ALU is ~ 10 K cells (synthesis runtime range from few seconds to ~5 min)

* small core (low-end) is ~1M cells (synthesis runtime range from 1~8 hours)

In the Intel terminology: "sea of FUBs" approach is to prefer small partitions, while "sea of cells" approach prefer big partitions.

About the predominance of latch or flop, it's mainly a consequence from the level of manual optimization. (latch are smaller, but harder to manage, and it give diminishing returns with new process node). Same for process-node-specific vs process-node-agnostic.

PS: Most modern designs are "sea of cells" according the Intel terminology