[emusan]

I think “low speed” is quite a relative term here. PCIe serdes lanes are for very high data rate communication (> 1gbps per lane). This is the realm of the Syzygy XCVR standard.

The lower speed Syzygy standard, while not operating at these speeds, is capable of much higher rates than a typical microcontroller. There are many peripherals with I/O requirements beyond a simple LED or SPI device, but below that of a PCIe or other high rate transceiver such has:

- moderate to high end ADCs and DACs (LVDS and parallel)

- image sensors (LVDS, parallel, and HiSPI)

- various networking PHYs

The lower end syzygy connector has pinouts to support LVDS differential pairs, which can easily achieve hundreds of Mbps data rates.

[Neywiny]

Piggy backing on this, image sensors using CSI are quite common. I don't know if anyone has this application, but theoretically if you wanted more than a few (I think even higher end processors cap out at 4) video streams in comes.... FPGAs. Maybe the newer Qualcomm XR chipsets can deal with that but an FPGA seems more attainable.

[bobmcnamara]

Qualcomm has supported CSI virtual channels for ages - you can get a little 4:1 bridge IC to renumber streams. IIRC, the 855 had 4 CSI IFEs, and would happily handle a 16x configuration if you bought the wide memory bus.