[mrlambchop]

I recently worked on a product (Realtek 200MHz MCU + integraiton wifi/ble) that had a similar setup - QSPI connected PSRAM and QSPI connected Flash (with read/write).

The PSRAM had a reasonable size page cache in the chip that made this memory quite responsive from a CPU perspective - a few rare cache flushes were needed, but things like DMA and bus masters (onboard radios etc..) were completely coherent and it made development much easier to manage.

My takeaway was that PSRAM was surprisingly capable (with the right can of hardware controller in place). Kudos to Realtek for getting the hardware to work without a thousand impossible to debug CPU lock ups...