[jaustin]

Looks like it's an "and" in silicon and an "or" at boot time?

>RP2350 includes a pair of open-hardware Hazard3 RISC-V cores which can be substituted at boot time for the Cortex-M33 cores. Our boot ROM can even auto-detect the architecture for which a second-stage binary has been built and reboot the chip into the appropriate mode

https://www.raspberrypi.com/documentation/microcontrollers/s...

[Narishma]

From what I've read, it's also possible to run one ARM core and one RISC-V core concurrently.

[tommiegannert]

Yes, the ARCHSEL register has one bit for each core.

Page 1274 of https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p....

[ClumsyPilot]

But how would that be practically usable?