[Zagitta]

It seems like a really strange choice to me that they made the arm and riscv cores mutually exclusive in each core complex since this just wastes die space on the core you're not using which in turn drives up the cost.

I feel like it would've been preferable if they either went all in on riscv or at least made it so all 4 cores could be used at the same time.

But if I were to guess the performance of the riscv cores probably doesn't match the ARM cores so they weren't confident enough in shipping a pure riscv SoC like espressif does.

Any other guesses as to why they might've gone this route?

[childintime]

Power consumption may be the lead motive here, as RISC-V cores are typically significantly more power efficient. This allows them to tap into markets they otherwise could not. The next gen will likely be RISC-V only though.

[brucehoult]

There is no need to guess, they've SAID that the simple RISC-v cores they're designed for it don't have FPU or SIMD like the Arm M33 does (the previous Pico's CM0 didn't have either), and the RISC-V core does 3.81 Coremark per MHz while the M33 does 4.09, so a 7% difference there.

Of course both are much better than the previous Cortex-M0+'s 2.46 Coremark/MHz, plus more MHz also: 150 vs 133.

[vardump]

M33 does not have SIMD. No Helium or anything else.

DSP extensions are included, but those are all scalar.