The 9950X seems more exciting than the last week's 9700X/9600X. It is comfortably ahead of the previous gen (including X3D) in code compilation and video/image processing, which I care about more than performance in games, and it's also in a class of its own in workloads heavy on AVX-512, though they might be a bit niche.
I think the TDP on the 9700X and 9600X may have been set a bit too low (in fact, there are indications it will be raised in a future BIOS update [1]), which led to a relatively cool reception from reviewers focused on raw performance. When looking at performance-per-watt in Phoronix tests, 9700X and 9600X often fare better than the bigger chips with higher TDP, but for desktops I guess efficiency is just not that big of a concern.
> and it's also in a class of its own in workloads heavy on AVX-512, though they might be a bit niche.
It'll be interesting to see if it remains niche - I do a fair bit of work on graphics rendering (some games, some not) and there's quite a bit in avx512 that interests me - even ignoring the wider register width. A lot of pretty common algorithms we use can be expressed a fair bit easier and simpler using some of those features.
Previous implementations either weren't available on consumer platforms, or had issues where they would downclock/limit ALU calculation width for some time after an avx512 instruction was run, only returning to full speed after a significant time - presumably when whatever power delivery issues could settle - which seriously affected what use cases in which it made sense. It wasn't worth it to have "small data set" users of avx512, as it would actually run slower than the equivalent avx2 code due to this. And the size of "large enough" data sets was pretty close to where it'll be better to schedule a task on the GPU anyway....
But AMD's implementation doesn't seem to have this problem - so this opens up the instruction set to much more use cases than previous implementations.
Or has the AVX512 ship already sailed? With Intel apparently being unable to fix these issues and started hacking it into even smaller bits? I mean, arguably they should have started with that - the register width is probably the least interesting part to me, but at some point having it actually widely adopted might be more useful than a "possibly better" version that no chip actually supports.
A TDP of 170 Watt is quite the beast. I don't think that it's reasonable to claim this isn't a major concern just because it's a desktop processor. This reflects in operational cost and anything directly and indirectly related to cooling, which means case size and noise.
Shout out to Michael Larabel for performing this much testing for every chip and distro, this close to their release, and with this thorough presentation every single time.
I honestly don't know how he does it. It seems like more testing than can fit in real time, even when running tests of different machines in parallel. His tooling and workflow must be dialed in to levels I can't imagine and YouTubers appear to have yet to reach.
Michael, you are a gift to the industry, thank you for doing all of this so well that we can take it for granted, and thank you for continuing to do it even though many do take it for granted.
timlatim|1 year ago
I think the TDP on the 9700X and 9600X may have been set a bit too low (in fact, there are indications it will be raised in a future BIOS update [1]), which led to a relatively cool reception from reviewers focused on raw performance. When looking at performance-per-watt in Phoronix tests, 9700X and 9600X often fare better than the bigger chips with higher TDP, but for desktops I guess efficiency is just not that big of a concern.
[1] https://videocardz.com/newz/amd-set-to-boost-tdp-for-ryzen-5...
kimixa|1 year ago
It'll be interesting to see if it remains niche - I do a fair bit of work on graphics rendering (some games, some not) and there's quite a bit in avx512 that interests me - even ignoring the wider register width. A lot of pretty common algorithms we use can be expressed a fair bit easier and simpler using some of those features.
Previous implementations either weren't available on consumer platforms, or had issues where they would downclock/limit ALU calculation width for some time after an avx512 instruction was run, only returning to full speed after a significant time - presumably when whatever power delivery issues could settle - which seriously affected what use cases in which it made sense. It wasn't worth it to have "small data set" users of avx512, as it would actually run slower than the equivalent avx2 code due to this. And the size of "large enough" data sets was pretty close to where it'll be better to schedule a task on the GPU anyway....
But AMD's implementation doesn't seem to have this problem - so this opens up the instruction set to much more use cases than previous implementations.
Or has the AVX512 ship already sailed? With Intel apparently being unable to fix these issues and started hacking it into even smaller bits? I mean, arguably they should have started with that - the register width is probably the least interesting part to me, but at some point having it actually widely adopted might be more useful than a "possibly better" version that no chip actually supports.
chipdart|1 year ago
rainclouds|1 year ago
fl0ki|1 year ago
I honestly don't know how he does it. It seems like more testing than can fit in real time, even when running tests of different machines in parallel. His tooling and workflow must be dialed in to levels I can't imagine and YouTubers appear to have yet to reach.
Michael, you are a gift to the industry, thank you for doing all of this so well that we can take it for granted, and thank you for continuing to do it even though many do take it for granted.
jrepinc|1 year ago