[robjwells]

Xtensa is from Tensilica (now Cadence) but, as sibling comments point out, new Espressif designs use RISC-V. There's a bit of an overlap point: the ESP32-S2 and ESP32-S3 are recent designs that use Xtensa, and they were released at roughly the same time as the ESP32-C3 (I believe the first Espressif RISC-V part).

Here's the ISA summary for Xtensa LX as used by the ESP32: https://www.cadence.com/content/dam/cadence-www/global/en_US...

The S2 & S3 are more powerful and capable than the currently available Espressif RISC-V microcontrollers. Perhaps it's best to think of them marking the summit or climax of Espressif's Xtensa parts. But the future clearly lies with RISC-V.

The Xtensa support in LLVM/Clang appears to have resulted (at least in part) from Espressif's active support for Rust on their microcontrollers. The recent Rust 1.81 release merged support for the ESP32, ESP32-S2 and ESP32-S3 into upstream rustc. It's great to see a microcontroller vendor directly support the use of Rust on its parts, and not just its "new" parts.

Edit: To be clear, the ESP-IDF framework is a huge C project, so Espressif working on LLVM support for Xtensa is clearly _not just_ for Rust. And "easy mode" Rust-on-Espressif (std support!) relies on the ESP-IDF so merging their patches into LLVM is beneficial all-round.