[claudio_mos]

That code in the figure is an old code, honestly it's an old screenshot that I don't even remember what it corresponds to, but your analysis is basically correct, even though I used absolute addresses before while now everything is relative to the current address. I'll try to answer a bit of everything:

- yes, R0 is constantly set to 0. - ANYI is a ternary function (ANY) that uses an immediate (ANYI). It does nothing but load the immediate value into the register indicated as the first operand. - Yes, it is a balanced ternary, and clearly negative addresses are correctly interpreted

>out 50(r0) r2 ;output on console0? out 60(r0) r2 ;output on console1?

- Exactly. 50 and 60 are the addresses of the two serial ports on the motherboard.

- R26 is the return register set by JSR

-Addressing is at tryte level and an instruction is always 4 trytes long. You are right that it seems a bit strange, but it is a compromise that I had to accept and that I think was the best solution to implement. (I am happy to note that your doubt was also our strong doubt during the design phase, it means that we are considering the same problems...)

-There are the dimensions of the data to operate on as a suffix of the instructions (like on motorola 68000) for which there is an LD.T (load tryte), LD.S (load short) and LD.W (load a whole word of 24 tries). There are also instructions that load/save by addressing the memory as if it were a stack for example PUSH.W (R20),R4

>Even again each instruction is 4 tries, so we could eliminate the low bits and >move... oh, I forgot that it is ternary, it does not matter. You think I didn't think about it? ;)

- The IO space is separate, in the end it cost me almost nothing and I did it.

The RISC features that I have kept are essentially 2: - Constant instruction length - Memory access only with Load/Store

In fact among the RISC things that I could remove in a future version are precisely the single access to memory only with LD/ST, it is true that it is a main feature of RISC, but it is also true that it could be a problem for code density. But it is something that I will see on the 48-trit architecture

>This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product.

-That it is "conventional" ok, (even if none of the conventional architectures are ternary, but whatever...) that it is messy, what do you mean? The website says what the project actually is. I'm glad they are grandiose things, but that's it. And yes, we want to become a commercial product soon. If you have suggestions or other specific questions, I'm here to answer you ;)

[rep_lodsb]

If there's a LD.T instruction, it would've been the obvious choice to use that to load a character, instead of wasting an entire word on each. But maybe it didn't exist yet when that code was written.

The console I/O also seems to be dependent on external hardware to delay until the last character has been actually sent, or maybe your prototype was clocked slow enough that this wasn't necessary?

So, if the external data bus is always 24 trits, however addressing is in units of 6 trits, how does the hardware (CPU->memory interface) handle that? Is the address bus using binary instead of ternary?

What I meant by "conventional" is that other than using base 3, it isn't that different from other computer architectures, certainly not the idea you describe in the OP (that must have come later, since it isn't mentioned at all on your website). Some ternary operations might be useful for neural nets, but that wouldn't be an application for a general-purpose processor like this.

And some of the "messiness" might have been fixed, but again, there is absolutely no specification of what this architecture is supposed to be, so I was going from the one snippet of code that you have made public. And maybe you're still making changes, or do you intend to market a commercial microprocessor with absolutely no published specification?

[claudio_mos]

Yes, of course to load a character I use LD.T

Uhmm..actually the OUT instruction ends immediately after its normal cycle. the character is sent to the mainboard that reads it and puts it in a buffer and passes from a buffer. (it's more complex, if you want we can discuss)

The external BUS is 24 trit. the motherboard converts it by encoding it into binary and the data is stored on 48bit RAM. We don't have native ternary RAM yet unfortunately, but it was the only way to have some memory and use the processor.

I don't quite understand what idea I describe in the OP you're referring to. And I don't understand what ternary operations might be useful for neural networks (we've had contact with Korean researchers asking about this processor for neural networks).

The specifications obviously exist, but I don't think it's a good idea to put them here on a generic site! I think the marketing phase will take a while longer and as you may have read on the site, we're still fixing things here and there and we need a marketing apparatus.