[claudio_mos]

Yes, the serial buffer is included in the motherboard. The problem is not so much for OUT but for IN, if the buffer fills up.

As for the bus addresses, the counter program starts from the lowest address. The mainboard obviously knows how much RAM is present and performs a translation to the first available low address. Nothing transcendental.

I did not understand the connection with VonNeumann architectures, this is a classic vonneumann architecture, only that the information is in base 3...

Anyway you seem to be really very expert, certainly more than me (I am mainly a programmer and I had to learn these things at low level practically by myself), you could actively help the project...

[rep_lodsb]

In your OP, you wrote that this ternary computer is really a "first step" towards a completely different dataflow-based architecture. The main page of your website proclaims some sort of revolutionary "Third Millenium Computing", with applications to AI and "research on algorithms", whatever that is supposed to mean.

>The mainboard obviously knows how much RAM is present and performs a translation to the first available low address.

How exactly is this done in hardware? I can't figure it out, so you must be the expert on that. Unless it's like a separate microcontroller doing div/mod in a loop to convert between the bases for every memory access, it couldn't be that, right? Right?

[claudio_mos]

Ok, maybe that's not clear, probably my not-so-perfect English is a problem. The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and ternary arithmetic. This may eventually form the basis for the dataflow processor, but right now I'm talking about and building the ternary processor (Of course dataflow architectures are quite different and unconventional, but that's in the future, I'm not talking about it now).

As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA. It already comes to the FPGA in "ternary encoded bunary" from external circuits.