[netr0ute]

This is basically irrelevant now that better ISAs like RISC-V have a fixed instruction length (2 or 4 bytes) so the fancy algorithm here isn't necessary.

[lifthrasiir]

That fancy algorithm is relevant to RISC-V (and in fact, most fixed-length ISAs) because loading an immediate into a register needs one or two instructions depending on the immediate; you surely want to elide a redundant LUI instruction if you can. Of course such redundant instructions don't harm by itself, but that equally applies to x86 as the algorithm is an optimization.

[Coolbeanstoo]

As a result of RISC-V existing, all x86 processors have ceased to exist or be produced.

[snvzz]

Accurate, if said sometime in the future rather than today.

[remexre]

This same problem applies to RISC-V with the C extension, because the J and JAL instructions have a larger range than the C.J and C.JAL instructions.

[tliltocatl]

Having fixed instruction length doesn't make the need to load large constants magically disappear. These just get split between multiple instructions. If anything, RISC-V might be worse. See also https://maskray.me/blog/2021-03-14-the-dark-side-of-riscv-li....

[nicebyte]

ARM would have been a better example because the amount of people that care about RISC-V is a rounding error compared to x86 or ARM.