[KenoFischer]

My understanding is that the TinyTapeout people were using efabless as a service provider and efabless was also providing some sponsorship, but that they are institutionally distinct. There's a LinkedIn post from the TinyTapeout folks that they're looking into alternatives.

[kragen]

That's a relief! And Tiny Tapeout has already done a beta with IHP's open-source 130nm BiCMOS SiGe PDK.

The IHP PDK is really a lot more exciting to me than the Skywater stuff because it's aimed at submillimeter analog things (450GHz fₜ, 650GHz fastest oscillator) and why would you fab a digital design in 130nm instead of just programming an FPGA?

[le-mark]

> why would you fab a digital design in 130nm instead of just programming an FPGA?

That’s an interesting concept. So an fpga implemented on a current 7nm process is more performant (clock speed and energy use) than an asic on a 130nm process? How about 40nm process? I feel like there’s a graph of intersecting lines here.

[willis936]

Radiation tolerance is one case. For the price of a tiny tapeout run you could count on one hand how many qualified radiation tolerant ICs you could buy. There's some sauce involved with process choices for radiation tolerance, but one of critical things to do is use large features.

[bgnn]

IHP is excitinybut their PDK is horrible compared to major fabs like TSMC or GF. Anyone using it for products hate it.

[15155]

> and why would you fab a digital design in 130nm instead of just programming an FPGA?

Because you need some analog features with your digital design.

[nickpsecurity]

You should really look into summaries on how deep sub-micron adds more problems as processes shrink. It's crazy that 28nm and under even work at all. They also break faster in more ways than larger, mature nodes.

Far as 130nm, I'll give you a few reasons I'd use one over a 7nm FPGA. This is a non-HW guy saying what he's heard from pro's at different times. HW people, feel free to correct me about whatever I get wrong.

1. Unit prices. If you can take the upfront cost (NRE), the per unit price will be much lower than FPGA's. You might charge plenty per unit depending on the market. This can be a source of profit.

2. Older, larger nodes are said to be better for analog. Lots of designs are mixed-signal to use analog for it's lower power, extra performance, or how it doesn't blink (no rise/fall with clock).

3. ASIC's can't be reprogrammed like FPGA's. The custom design might be more secure like Sandia Secure Processor (Score) or CHERI RISC-V. FPGA's can only do one of these except for antifuse FPGA's.

4. Larger nodes are easier to visually inspect for backdoor with cheaper, teardown hardware. Who knows what's in the FPGA's.

5. Larger nodes are easier to synthesize, P&R, and auto-inspect (eg Calibre). That means open-source tools have a better chance of working or even being developed.

6. If not too power hungry (or power is cheap), some applications can let you outperform 7nm parts with parallel use of 130nm parts which are much cheaper or highly-optimized. An example what media wanting to do distributed, massively-parallel design for doing NN training maybe with 8-bitters and on-board, analog accelerators. My inspiration, aside from old MPP clusters (eg Thinking Machines), was a wafer-scale, analog NN done before Cerebras.

7. Improved reliability in general. In trusted checkers or fault-tolerant configuration, I feel like the 130nm parts are less likely to have a double failure or fail before the 7nm nodes.

8. If there's a business case, saying you built your own hardware is cool. It might even attract talent who benefit the company in other ways.

That's off the top of my head. Again, I just read a lot of stuff on ASIC's.

On a side note, you might find eASIC's Nextreme's interesting. They're Structured ASIC's that work like FPGA's in that design gets put on something with pre-made blocks to save money. Except, instead of software programmed, some via or metal layers get customized for the routing. While that reduces NRE cost, doing the routing in hardware supposedly reduces unit prices and energy maybe with a performance boost. They used to sample chips out quickly and relatively cheaply. Also, I think Triad Semiconductor had S-ASIC's with analog stuff.

[genewitch]

wait, does 130nm imply i can send them verilog and receive ASICs in the mail?