[dcan]

To be more precise, four CPUs - two ARM and two RISC. There is just a mux for the instruction and data buses - see chapter 3 of the [datasheet](https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.p...).

It’s space-inefficient as half of the CPUs are shutdown, but architecturally it’s all on the same bus.

[Aurornis]

> It’s space-inefficient as half of the CPUs are shutdown

In practice is doesn't matter very much for a design like this. The size is already limited to a certain minimum to provide enough perimeter area to provide wire bonding area for all of the pins, so they can fill up the middle with whatever they want.

[DrNosferatu]

They should have filled it with more SRAM instead - 520KB is far too little.

[Narishma]

It may be technically space inefficient but they only added the RISC-V cores because they had area to spare. It didn't cost them much.

[enragedcacti]

Source for the RISC-V cores being essentially free (Luke Wren is the creator of the RISC-V core design used):

> The final die size would likely have been exactly the same with the Hazard3 removed, as std cell logic is compressible, and there is some rounding on the die dimensions due to constraints on the pad ring design.

https://nitter.space/wren6991/status/1821582405188350417

[Graziano_M]

Funny thing is that it cost them more than you might think. It was the ability to switch to the riscv which made it (much) easier to glitch. See the "Hazardous threes" exploit [1]

[1] https://www.raspberrypi.com/news/security-through-transparen...

[petertodd]

I wonder if they're using the same die for one or more microprocessor products that are RISC-V-only or ARM-only? They could be binning dies that fail testing on one or the other cores that way. Such a product might be getting sold under an entirely different brand name too.

[myrmidon]

I find this whole concept remarkable, and somewhat puzzling.

Have seen the same (ARM + RISC-V cores) even at larger scales before (Milk-V Duo @1GHz-ish). But how is this economical? Is die space that cheap? Could you not market the same thing as quadcore with just minor design changes, or would that be too hard because of power budget/bus bandwidth reasons?

[imtringued]

SRAM is very area intensive. What you're asking for is very greedy. The RISC-V core they are using is absolutely tiny.

[bananapub]

two things:

1) it needs a certain perimeter to allow all the pins to go from the silicon to the package, which mandates a certain sized square-ish die 2) only the cores are duplicated (and some switching thing is added)

so yes, there is enough space to just add another two cores without any worries, since they don't need more IO or pins or memory or anything.