It's interesting to see a very x86_64-like attempt to shake off the weirdness of the ancestral architecture here. The PC is no longer an addressable register. Thumb has been dropped. The predication bits are no more. The weird register aliasing thing done by NEON is gone too. The register banking (and it seems most of the interrupt architecture) is entirely different.
And, just like in the Intel world, market pressures have introduced all new CISC quirks: AES and SHA256 instructions, for example.
But of course an architecture document does not a circuit make. All the weirdness (old and new) needs to be supported for compatibility (OK, maybe they can drop Jazelle), so the fact that they no longer talk about some things doesn't really save them any transistors in practice.
Honestly, this is sounding more like an Intel or AMD part, not less.
Is having hardware acceleration for AES and SHA256 really a "CISC quirk", or just a really specialized set of arithmetic instructions? The classic RISC idea of making the core simple and fast doesn't really apply here; internally, it's all simple micro-operations driving special-purpose hardware. It seems similar to having a fused multiply-accumulate operation: they've figured out how to accelerate the core of a common task, and this is the API they've decided to give it.
Yes, its too bad cleaning up the architecture doesn't necessarily cleanup the physical design. As GPUs have been more recent entrants to the general purpose space it is clear they are trying to avoid the same mistakes. The only place you will find a a true GPU binary is buried deep in the memory of the runtime stack (for NVIDIA at least, not sure about AMD).
> The one surprise in ARMv8, is the omission of any explicit support for multi-threading. Nearly every other major architecture, x86, MIPS, SPARC, and Power has support for multi-threading and at least one or two multi-threaded implementations.
What does this even mean? Are they talking about atomic operations? Hyperthreading?
I don't see how it could be about hyperthreading, since that's a CPU implementation detail and mostly unrelated to the instruction set. Maybe it's referring to specifying memory consistency behavior and support.
A question about how HN works. I'd submitted the same article to HN at a much less opertune time so it fell off the "new" page before it got its first upvotes. [1]
Normally when somebody then resubmits the same article at a better time I thought they had to add a '~' at the end of the URL or something, but I don't see anything like that in this case. So how'd they do it?
(And I should say I'm glad that you all get to see this article, so thank you enos_feedler).
Honest question since I'm confused about terminology: Why is ARMv8 described in places as "backwards compatibility for existing 32-bit software" when some existing instructions will be removed in AArch64?
It looks like an interesting article, so it is a shame that it was split into 5 pages with no way to view everything on one page. I have no recourse but to not read the article at all.
> I have no recourse but to not read the article at all
You could click the next button 4 times and read the full article. There's lots of content on each page. It would've taken 100% less typing than this complaint, and you would've spent that time learning instead of grumbling.
It's a real shame you can't read books either. Whole libraries of documents split into pages with no "view all" button.
It scrapes down and combines multi-page articles like this with a click for on or offline reading. Great interface and mobile apps too, I use it all the time.
[+] [-] ajross|13 years ago|reply
And, just like in the Intel world, market pressures have introduced all new CISC quirks: AES and SHA256 instructions, for example.
But of course an architecture document does not a circuit make. All the weirdness (old and new) needs to be supported for compatibility (OK, maybe they can drop Jazelle), so the fact that they no longer talk about some things doesn't really save them any transistors in practice.
Honestly, this is sounding more like an Intel or AMD part, not less.
[+] [-] pjscott|13 years ago|reply
[+] [-] unknown|13 years ago|reply
[deleted]
[+] [-] enos_feedler|13 years ago|reply
[+] [-] klodolph|13 years ago|reply
What does this even mean? Are they talking about atomic operations? Hyperthreading?
[+] [-] Symmetry|13 years ago|reply
http://www.mips.com/products/architectures/application-speci...
[+] [-] TwoBit|13 years ago|reply
[+] [-] enos_feedler|13 years ago|reply
[+] [-] Symmetry|13 years ago|reply
Normally when somebody then resubmits the same article at a better time I thought they had to add a '~' at the end of the URL or something, but I don't see anything like that in this case. So how'd they do it?
(And I should say I'm glad that you all get to see this article, so thank you enos_feedler).
[1]http://news.ycombinator.com/item?id=4380604
[+] [-] parenthesis|13 years ago|reply
[+] [-] vdondeti|13 years ago|reply
[+] [-] rogerbinns|13 years ago|reply
I'd also be curious if it was possible to software translate 32 bit arm binaries into 64 bit while retaining comparable performance.
[+] [-] lunarscape|13 years ago|reply
[+] [-] Symmetry|13 years ago|reply
[+] [-] rblackwater|13 years ago|reply
[+] [-] dangrossman|13 years ago|reply
You could click the next button 4 times and read the full article. There's lots of content on each page. It would've taken 100% less typing than this complaint, and you would've spent that time learning instead of grumbling.
It's a real shame you can't read books either. Whole libraries of documents split into pages with no "view all" button.
[+] [-] smashing|13 years ago|reply
[+] [-] incision|13 years ago|reply
It scrapes down and combines multi-page articles like this with a click for on or offline reading. Great interface and mobile apps too, I use it all the time.