This is not a good article and the content doesn't support the claim in the title. It talks about memory latency and how it negatively affects instruction level parallelism, but doesn't offer any solution or advice, except for offering their own (payed) service...
adrian_b|9 months ago
Otherwise the performance is limited by the memory transfer throughput, not by the latency of individual memory accesses.
The article demonstrates the difference between these 2 cases, even if its title could have been better.
Because the latency of memory loads is many times greater than the latency of any other kind of CPU instructions, both for loads from the main memory and for loads from the L3 cache memory, this effect is more visible in programs with many memory loads, like the examples from the article, than in programs using other instructions with long latencies.
jjtheblunt|9 months ago